ASQED 2009 Final Program
Wednesday July 15 2009
2:00PM-3:30PM NIRWANA Ballroom 2A
Advanced Memory and Special Circuit Techniques
Chair: Volkan Kursun
Co-Chair: Dennis Wong
2:00PM
1A.1
Mutual Exploration of FinFET Technology and Circuit Design Options for Implementing Compact Brute-Force Latches
Sherif Tawfik1 and Volkan Kursun2
1University of Wisconsin-Madison, 2The Hong Kong University of Science and Technology
2:30PM
1A.2
A High Speed Subthreshold SRAM Cell Design
Amir Reza Ahmadi Mehr, Behzad Ebrahimi, Ali Afzali Kusha
University of Tehran
2:50PM
1A.3
Realistic CNFET Based SRAM Cell Design for Better Write Stability
Behzad Ebrahimi and Ali Afzali Kusha
University of Tehran
3:10PM
1A.4
A Comparison Study of the effects of Supply Voltage and Temperature on the Stability and Performance of CNFET and Nanoscale Si-MOSFET SRAMs
Mahdi Moradinasab and Morteza Fathipour
University of Tehran
Wednesday July 15 2009
2:00PM-3:30PM NIRWANA Ballroom 2B
Multi-gate Devices and Manufacturing
Chair: Anatoli Vakhguelt
Co-Chair: L C Tan
2:00PM
1B.1
Process-Variation- and Random-Dopant-Induced Static Noise Margin Fluctuation in Nanoscale CMOS and FinFET SRAM Cells
Tien-Yeh Li, Chih-Hong Hwang, Yiming Li
National Chiao Tung University
2:30PM
1B.2
Analytical Modeling of Hot Carrier Injection Induced Degradation in Triple Gate Bulk FinFETs
Nayereh Ghobadi, Ali Afzali-Kusha, Ebrahim Asl-Soleimani
School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
2:50PM
1B.3
A Novel 4H-SiC UMOSFET_ACCUFET with large Blocking Voltage
Negin Peyvast and Morteza Fathipour
Device and Process Modeling and Simulation Lab., School of Electrical and Computer Eng., University of Tehran, North Kargar Ave., Tehran, IRAN
3:10PM
1B.4
MEMS vs. IC Manufacturing: Is integration between processes possible
Vemal Raja Manikam, Kar Yoke Ong, Wai Yew Lo, Boon Seong Lee, Cheng Choi Yong
Freescale Semiconductor
Wednesday July 15 2009
2:00PM-3:30PM NIRWANA Ballroom 2C
Power Delivery, Packaging and PCB Technology
Chair: Joseph Fjelstad
Co-Chair: Farhang Yazdani
2:00PM
1C.1
Challenges in High Density PCB with 0.40 mm pitch BGA - from Design, fabrication & Assembly perspective
Pang Tun Leaw and Chee Peng Lim
Motorola
2:30PM
1C.2
Next Generation I/O Power Delivery Design through SIPD co-analysis & Comprehensive Platform Validation
Yee Hung See Tau and Marcus Chan
Intel Microelectronics (M) Sdn Bhd
2:50PM
1C.3
PCB Via Depth Effect on SSN for FPGA
Chin Pheing Wong, Pui Ling Lee, Wei Wei Lo, Man On Wong
Altera Corporation
3:10PM
1C.4
Measurement of worst-case power delivery noise and construction of worst case current for graphics core simulation
Fern Nee Tan
Intel Microeletronics (M) Sdn Bhd
Wednesday July 15 2009
4:00PM-6:00PM NIRWANA Ballroom 2A
Low-power and Noise-aware Design Innovations
Chair: Volkan Kursun
Co-Chair: Suphachai
Sutanthavibul
4:00PM
2A.1
Ground Bouncing Noise Suppression Techniques for MTCMOS Circuits
Hailong Jiao and Volkan Kursun
The Hong Kong University of Science & Technology
4:30PM
2A.2
Capacitive and Inductive Couplings in a Distributed RLC Interconnection Line: Additivity Waveforms
Denis DESCHACHT1 and Yves QUERE2
1CNRS-University Montpellier, France, 2University Brest, France
5:00PM
2A.3
Power Optimization in Multipliers Using Multi-Precision Combined with Dynamic Voltage Scaling Techniques
Xiaoxiao Zhang1, Amine Bermak1, Farid Boussaid2
1HKUST, 2UWA
5:20PM
2A.4
A Power Efficient Digitally Programmable Delay Element for Low Power VLSI Applications
Sekedi Bomeh Kobenge and Huazhong Yang
NICS, Department of Electronic Engineering, Tsinghua University, Beijing, P.R.C
5:40PM
2A.5
First Intel Low-Cost IA Atom-based System-On-Chip for Nettop/Netbook
Suphachai Sutanthavibul1 and Perabala Suresh Kumar2
1Intel Corp, 2Intel Microelectronics, Penang, Malaysia
Wednesday July 15 2009
4:00PM-6:00PM NIRWANA Ballroom 2B
Noise, Reliability, and Variability
Chair: David Pan
Co-Chair: Yu Wang
4:00PM
2B.1
Novel Variation Aware STA Methodology
Shigeru Kuriyama, Atsushi Yoshikawa, Genichi Tanaka
Renesas Technology Corp.
4:30PM
2B.2
On Minimizing Various Sources of Noise and Meeting Symmetry Constraint in Mixed-Signal SoC Floorplan Design
Chung-Hsin Lin1 and Hung-Ming Chen2
1Anpec Electronics Cor., Taiwan, 2Dept of EE, NCTU, Taiwan
5:00PM
2B.3
Comparative Analysis of Process Variation Impact on Flip-Flops Soft Error Rate
Hassan Mostafa, Mohab Anis, Mohamed Elmasry
University of Waterloo
5:20PM
2B.4
The Impact of Timing Yield Improvement Under Process Variation on Flip-Flops Soft Error Rate
Hassan Mostafa, Mohab Anis, Mohamed Elmasry
University of Waterloo
5:40PM
2B.5
Statistical Model for Ring Oscillator Phase Noise Variability Accounting for Within-Die Process Variation
Faizal Khalek1, Hassan Mostafa2, Mohab Anis2
1Multimedia University, Malaysia, 2University of Waterloo, Canada
Wednesday July 15 2009
4:00PM-6:00PM NIRWANA Ballroom 2C
Nano and Bio Electronics Innovations
Chair: Yiming Li
Co-Chair: Tanay Karnik
4:00PM
2C.1
Propagation Delay Dependence on Channel Fins and Geometry Aspect Ratio of 16-nm Multi-Gate MOSFET Inverter
Hui-Wen Cheng, Chih-Hong Hwang, Yiming Li
National Chiao Tung University
4:30PM
2C.2
An AER-based CMOS Polarization Image Sensor with Photo-Patterned Micropolarizer Array
Xiajun Wu1, XiaoJin Zhao1, Amine Bermak1, Farid Boussaid2
1Hong Kong University of Science and Technology, 2University of Western Australia
5:00PM
2C.3
An Analytic Channel Potential Based Model for Dynamic Depletion Surrounding-Gate MOSFETs with Arbitrary Doping Level
Lining Zhang, Jian Zhang, Feng Liu, Frank He
IME,PKU,China
5:20PM
2C.4
New Challenges on Leakage Current Improvement in Tunnel FET by Using Low-K Oxide
Mahdi Vadizadeh, Morteza Fathipour, Benyamin Davaji
Dept of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
5:40PM
2C.5
Numerical Study of Scaling Issues of C-CNTFETs
Farshid Karbassian, Mahdi Moradinasab, Morteza Fathipour
University of Tehran
Thursday July 16 2009
8:00AM-9:30AM NIRWANA Ballroom 2A
Photovoltaic Technology & Manufacturing
Chair: Yiming Li
Co-Chair: Ali Iranmanesh
8:00AM
3A.1
Embedded Analog CMOS Neural Network Inside High Speed Camera
Brahmantyo HERUSETO1, Eri PRASETYO1, Hamzah AFFANDI1, Michel PAINDAVOINE2
1Gunadarma University, Indonesia, 2Burgundi University, France
8:30AM
3A.2
Design of Digital Display System for ISFET pH sensor by using PIC Microcontroller Unit (MCU)
Muhammad Naim Haron and Uda Hashim
Institute of Nano Electronic Engineering (INEE)
8:50AM
3A.3
A Unified Parameterization Technique for TFT-LCD Panel Design Optimization
Hsuan-Ming Huang and Yiming Li
National Chiao Tung University
9:10AM
3A.4
Improving Performance in Single Field Plate Power High Electron Mobility Transistors (HEMTs) based on AlGaN/GaN
Morteza Fathipour1 and reza azadvari2
1Author, 2
Thursday July 16 2009
11:00AM-12:30PM NIRWANA Ballroom 2A
Analog and Low Power Test
Chair: Fakhrul Rokhani
Co-Chair: Serge Demidenko
11:00AM
4A.1
Towards Formal Verification of Analog Mixed Signal Designs using SPICE Circuit Simulation Traces
Kusum Lata1, Subir Kumar Roy2, H. S. Jamadagni1
1CEDT, Indian Institute of Science, Bangalore, India., 2Texas Instruments (India) Private Limited, Bangalore, India.
11:30AM
4A.2
Prototyping and Testing of Analog Integrated Circuits
Peter Pann
austriamicrosystems AG
11:50AM
4A.3
A Self-Testing Method for Combinational Circuits Using Polymorphic Gates
Hassan Hatefi Ardakani and Morteza Mashayekhi
KIAU
12:10PM
4A.4
Scan-chain Masking Technique for Low Power Circuit Testing
Subhadip Kundu and Santanu Chattopadhyay
IIT Kharagpur
Thursday July 16 2009
11:00AM-12:30PM NIRWANA Ballroom 2B
Misc. Design Topics
Chair: Lee Kee Yong
Co-Chair: Ali Iranmanesh
11:00AM
4B.1
Novel Low Delay Slew Rate Control I/Os
Vikas Narang, Arya B, Karthik Rajagopal
Texas Instruments, India
11:04AM
4B.2
Low Cost Clock Cleaner Solution for Reference Clock Sources
Han Chin How, Chong Ling Khoo, Wei Wei Lo, Man On Wong
Altera Corporation
11:08AM
4B.3
OFF Stage Leakage Analysis from Power Gating Application In Deep Sub-micron Technology
Lee Kee Yong
Intel inc.
11:12AM
4B.4
AREA-EFFECTIVE PROGRAMMABLE FSM-BASED MBIST FOR SYNCHRONOUS SRAM
Nur Qamarina Mohd Noor1, Yusrina Yusof1, Azilah Saparon1, Mahmud Adnan2
1UiTM Shah Alam, 2INTEL Malaysia
11:16AM
4B.5
Self Centering Assessment of Stacked CSP Memory Components
Satyanarayan Iyer1, Gurudutt Chennagiri1, Abd Aziz Ali Akhbar2, Amran Ismail2
1SMART Modular Technologies, Inc., CA, USA, 2Smart Modular Technologies Sdn. Bhd., Penang, Malaysia
11:20AM
4B.6
How Organic Substrate Structure & Design Improve Assembly Robustness
Boon Yew Low and Ravishankar Sankaran
Freecscale Semiconductor M Sdn Bhd
11:24AM
4B.7
Platform Stitching Capacitors Impact to High-Speed Differential Links on Non-Ideal Return Path
Kai Lun Ching1, Chee Kheong Yoon1, Teong Guan Yew1, Fabian Wai Lee Kung2, Hin-Yong Wong2, Gobi Vetharatnam2
1Intel Microelectronic Sdn. Bhd., 2MMU
11:28AM
4B.8
Investigation of Low Vbd on 7nm Oxide POD Capacitor
Hong Seng Ng
X-Fab Sarawak
11:32AM
4B.9
Accurate Defect Cluster Detection and Localisation on Fabricated Semiconductor Wafers using Joint Count Statistics
Melanie Ooi, Ye Chow Kuang, Wey Jean Tee, Achath Mohanan Ajay, Chris Chan
Monash University
11:36AM
4B.10
I-V characteristics of a ZnO thick-film varistor fabricated by cold-pressing method
mohammad orvatinia1 and Saeed Gandomkar22
1ICT faculty, Tehran/Iran, 2Islamic Azad university of Busher, Busher/Iran
11:40AM
4B.11
Indium Phosphide, Indium-Gallium-Arsenide and Indium-Gallium-Antimonide based High Efficiency Multijunction Photovoltaics for Solar Energy Harvesting
Indranil Bhattacharya and Simon Y. Foo
Florida State University
11:44AM
4B.12
Novel Techniques for Off-State Current Components Reduction in Double Gate Source-Heterojunction-MOS-Transistor
Mahsa Tahermaram, Morteza Fathipour, Hamdam Ghanatian, Mahdi Vadizadeh
Dept of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
11:48AM
4B.13
Parameter Space Exploration for Robust and High-Performance n-Channel and p-Channel Symmetric Double-Gate FinFETs
Sherif Tawfik1 and Volkan Kursun2
1University of Wisconsin-Madison, 2The Hong Kong University of Science and Technology
11:52AM
48.14
Analytical Study of Drift Velocity in N-type Silicon Nanowires
Amir Hossein Fallahpour, Mohammad Taghi Ahmadi, Hassan Jafari, Razali Ismail
University Technology Malaysia
11:56AM
4B.15
Effect of Local Random Variation on Gate-Level Delay and Leakage Statistical Analysis
Jae Hoon Kim
Pohang University of Science and Technology, Pohang, Republic of Korea
12:00PM
4B.16
Incremental Optimization of Power Pads Based on Adjoint Network Sensitivity
Jairam S and Subir K Roy
SDTC, TI India
12:04PM
4B.17
hybrid functional verification methodology for Video & Audio Soc
Sandeep Gupta
Mentor Graphics
12:08PM
4B.18
An MTCMOS Power Network Design Flow
Yijia Xu and Gary Yeap
Synopsys Inc.
12:12PM
4B.19
MEBRS:Energy Balancing Route Scheduling in Centralized Wireless Sensor Networks
yawen dai1, quan wang2, xiaoqiang li1
1Wuhan University of Technology, 2Chongqing University of Posts and Telecommunications
12:16PM
4B.20
Simulation Study on NMOS Gate Length Variation Using TCAD Tool
Rahmat Sanudin, Marlia Morsin, Muhammad Suhaimi Sulong, Mohd Helmy Abd Wahab
Universiti Tun Hussein Onn Malaysia
Thursday July 16 2009
1:30PM-3:300PM NIRWANA Ballroom 2A
CMOS Imagers and Data Converters
Chair: Dennis Wong
Co-Chair: Amine Bermak
1:30PM
5A.1
A Programmable Compact Control Mechanism for Ultra-Low Power Current-Mediated CMOS Imagers
Fang Tang and Amine Bermak
HKUST
2:00PM
5A.2
A Low Power Linear Output Current-Mediated CMOS Imager
Fang Tang and Amine Bermak
HKUST
2:30PM
5A.3
6-bit 1.6GS/s ADC with low input capacitance in a 0.18um CMOS
Chun-Chieh Chen, Yu-Lun Chung, Chen-I Chiu
Department of Electronic Engineering, Chung-Yuan Christian University.
2:50PM
5A.4
500MS/s 4-b time interleaved SAR ADC using novel DAC architecture
Sanjay Talekar1, S. Ramasamy1, G. Lakshminarayanan2, B. Venkataramani2
1Mr., 2Dr.
3:10PM
5A.5
Design of Low Power and high speed reconfigurable resolution two step flash ADC
Mahesh Kumar A, Sreehari Veeramachaneni, M.B. Srinivas
International Institute of Information Technology ( IIIT),Gachibowli, Hyderabad, (A.P.), INDIA - 500 032
Thursday July 16 2009
1:30PM-3:300PM NIRWANA Ballroom 2B
Physical and System Design
Chair: Yu Wang
Co-Chair: David Pan
1:30PM
5B.1
X-architecture Clock Tree Construction Associated with Buffer Insertion and Sizing
Chia-Chun Tsai1, Chung-Chieh Kuo2, Trong-Yen Lee2, Jan-Ou Wu3
1Nanhua University, 2National Taipei University of Technology, 3De Lin Institute of Technology
2:00PM
5B.2
A Method for Improved Final Placement Employing Branch-And-Bound with Hierarchical Placement Encoding and Tightened Bounds
Xitian Li1 and John Lillis2
1ECE Dept of University of Illinois at Chicago, 2CS Dept of University of Illinois at Chicago
2:30PM
5B.3
Reliability-aware Global Routing under Thermal Considerations
Katrina Lu1 and David Z. Pan2
1Intel, 2University of Texas at Austin, ECE Dept
2:50PM
5B.4
Memory-Aware Power Modeling for PAC DSP Core
Chen-Wei Hsu1, Jia-Lu Liao1, Jen-Chieh Yeh2, Ji-Jan Chen2, Shi-Yu Huang1, Jing-Jia Liou1
1National Tsing Hua University, Taiwan, 2SoC Technology Center, Industrial Technology Research Institute, Taiwan
3:10PM
5B.5
Power Analysis of Hardware Based Motion Estimation in a Heterogeneous Reconfigurable Environment
Moazzam Hussain1 and Muhammad Mohsin Rahmatullah2
1Student @ CASE, Islamabad, 2Faculty @ CASE, Islamabad
Thursday July 16 2009
4:00PM-6:00PM NIRWANA Ballroom 2A
Advanced Topics in Design
Chair: SK Fong
Co-Chair: Dennis Wong
4:00PM
6A.1
A Proof of Concept on Defending Cold Boot Attack
Joo Guan Ooi and Kok Horng Kam
Intel Microelectronics Sdn Bhd
4:30PM
6A.2
A Reversible MIPS Multi-cycle Control FSM Design
Dilip Vasudevan, Maziar Goudarzi, Emanuel Popovici, Michel Schellekens
CEOL,University College Cork
5:00PM
6A.3
An Adjustable Reset Pulse Phase Frequency Detector for Phase Locked Loop
Lip-Kai Soh and Yew-Fatt Kok Edwin
Altera Corporation
5:20PM
6A.4
Variable Voltage Reference using Feedback Control Technique
Anshul Agarwal and Satyam Mandavilli
CVEST, International Institute of Information Technology-Hyderabad
5:40PM
6A.5
A CMOS Radio Frequency Receiver for Bluetooth Applications
Jenn-Tzer Yang
Ming-Hsin University of Science and Techonology
Thursday July 16 2009
4:00PM-6:00PM NIRWANA Ballroom 2B
Semiconductor Technology & Manufacturing
Chair: Anatoli Vakhguelt
Co-Chair: Cheah Soo Lan
4:00PM
6B.1
Modeling of Temperature Variations in MOSFET Mismatch for Circuit Simulations
Muhamad Amri Ismail1, Iskhandar Md Nasir1, Razali Ismail2
1MIMOS Berhad, 2Universiti Teknologi Malaysia
4:30PM
6B.2
Digital Pressure Sensor with Filtered Frequency Output Using Ring Oscillator and Mixer
James Yang1, Zhiping Yu1, Litian Liu1, Zhaohua Zhang1, Roy Liu2, Yafei Bi2
1Institute of Microelectronics, Tsinghua University, Beijing 100084, P.R. China, 2Lionax Technology USA Corporation
5:00PM
6B.3
A Numerical Study of Silicon Opening Process
Benyamin Davaji, Morteza Fathipour, Mehdi Vadizadeh
Dept of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
5:20PM
6B.4
A Novel Trench IGBT with a Rectangular Oxide beneath the Trench Gate
Jae In Lee, Jongchan Choi, Young-seok Bae, Man Young Sung
Department of Electrical Engineering, Korea University
5:40PM
6B.5
Structured Database Standardisation Framework for Data Mining of Semiconductor Manufacturing Data
Ajay Achath Mohanan1, Chris Chan2, Melanie Ooi1
1Monash University, 2Freescale Semiconductor
Thursday July 16 2009
4:00PM-6:00PM NIRWANA Ballroom 2C
Test & Verification
Chair: Serge Demidenko
Co-Chair: Fakhrul Rokhani
4:00PM
6C.1
Automatic Error Recovery in Targetless Logic Emulation
Somnath Banerjee and Tushar Gupta
Mentor Graphics Pvt. Ltd, India
4:30PM
6C.2
Combined Fault-Model Free Cause-Effect and Effect-Cause Fault Diagnosis in Block-Level Digital Networks
Raimund Ubar, Sergei Kostin, Jaan Raik
Tallinn University of Technology
5:00PM
6C.3
An Automated Approach for the Diagnosis of Multiple Faults in FPGA Interconnects
Nandha Kumar T and Sue Inn Ch'ng
Faculty of Engineering, The University of Nottingham Malaysia Campus, Selangor, Malaysia.
5:20PM
6C.4
Extraction based Verification Method for Off The Shelf Integrated Circuits
Daniel Saab1, Fatih Kocan2, Vivek Nagubadi1, Jacob Abraham3
1Case Western Reserve University, 2SMU, 3University of Texas at Austin
5:40PM
6C.5
Verification of Trace Length and Trace Impedance of Fabricated Load Board Using TDR
Sew Ming Low1, Michael Phoon2, Abu Suffian3, - Johan3
1Monash University Malaysia, 2Freescale Semiconductor Malaysia, 3
