A novel variation-aware STA methodology with a 65nm process is proposed. Statistical STA has come into use in order to consider process variation. But methodologies to consider SI such as crosstalk and PI such as voltage drop are still under investigations. However in the point of PI, process variations are considered definitely [1-3]. With the power shut off circuit, it is important to recognize variation of which part in the circuit, power routing, normal transistors, or switch transistors is most sensitive to performance. From this acknowledgement, it is necessary to control variation of most sensitive elements and develop validation flow to handle these phenomena. In this paper, process variation impact on the power shut off circuit is analyzed.　It is simulated that the variation of transistors' gate lengths, and the one of power routing resistance affect performance. With our methodology, the degree of performance variation margin can be reduced by 75% compared to previous method. Also we propose STA methodology of power shut off circuit with variation.