In deeply pipelined synchronous systems, any violation in the timing constraints of the flip-flops can cause the overall system to malfunction. Due to CMOS technology scaling, increased process variations result in large delay variability causing unacceptable loss in the timing yield. Several variation tolerant techniques were introduced to mitigate this variability challenge by improving the timing yield. In the mean time, devices are getting smaller, faster, and operating at lower supply voltages. These reduced capacitances and power supply voltages combined with the increased chip density to perform more functionality increase the soft errors susceptibility and make it one of the essential design challenges. Moreover, there are many flip-flops topologies that vary in their relative performance and power consumption which make the selection decision very difficult to flip-flops designers especially under variability and soft errors challenges.
Therefore, a comparative analysis between these different flip-flops topologies considering these scaling challenges will be beneficial to guide the flip-flops designers in selecting the best topology for their specific application. This paper presents a comparative analysis of timing yield improvement impact on flip-flops soft error rate in 65-nm CMOS technology. The analyzed flip-flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. Following that, they are compared for the soft error susceptibility. Moreover, it will be shown that the timing yield improvement increases the flip-flop soft error immunity significantly.