Nur Qamarina Mohd Noor1,  Yusrina Yusof1,  Azilah Saparon1,  Mahmud Adnan2
1UiTM Shah Alam, 2INTEL Malaysia


As the memory enters submicron technology, new test algorithms that will be able to give a better fault coverage such as to detect single-cell fault and all intra-word coupling fault (CF) have been widely developed. In order to implement this algorithm to the memory, test techniques such as BIST are utilized. Common types of programmable memory built-in-self tests (PMBIST) are microcode-based PMBIST and FSM-based PMBIST. The popular approaches of designing various kinds of PMBIST architectures are either by targeting to reach specific testing requirement such as full speed and at speed or by considering the cost-constraint and area overhead for low-cost or low-area design. In this paper, FSM-based BIST is designed to enable detecting both single-cell dynamic fault such as read destructive fault (RDF), deceptive read destructive fault (DRDF), and all intra-word coupling faults (CF) in a synchronous SRAM under low-area constraint of test requirement.