This paper presents an investigation of low oxide breakdown voltage on Polysilicon-Oxide-Diffusion (POD) capacitor. The dielectric was 7nm thermal oxide which was grown simultaneously for MOS transistor as gate oxide. The V-Ramp measurement showed bimodal distribution of Vbd with one circular patch having <7V instead of the target Vbd (10V). The size of the patch depends on the POD capacitor area. This behavior was not observed on gate oxide of MOS transistor and 22.5nm POD capacitor. Process partition check, including wafer orientation and wafer slot arrangement was conducted. The specific process step causing the patch signature has been identified successfully.