Scan-chain Masking Technique for Low Power Circuit Testing

Subhadip Kundu and Santanu Chattopadhyay
IIT Kharagpur


This paper addresses the issue of blocking pattern selection to reduce both leakage and dynamic power consumption during circuit testing using scan-based approach. The blocking pattern is used to prevent the scan-chain transitions to reach circuit inputs. This though reduces dynamic power significantly, can result in quite an increase in the leakage power. We have presented a novel approach to select a blocking pattern using Genetic Algorithm and use it properly so that both dynamic and leakage power is reduced. The avg. improvement in dynamic power is 20.4% and 10.8% in the case of leakage power (best is around 97.0% and 22.8% respectively) with respect to full scan circuit.