Various technology and design options based on independent-gate bias, work-function engineering, and gate-drain/source overlap engineering are explored in this paper to achieve compact multi-threshold voltage (multi-Vth) brute force FinFET latches. The different multi-Vth FinFET circuits are characterized and compared for active mode power consumption, propagation delay, setup time, leakage power consumption, layout area, and static noise margin. The clock power is minimized with the multi-Vth latches that combine the independent-gate bias and gate underlap engineering techniques. Alternatively, the total active mode power and the leakage power are minimized with the multi-Vth latches that combine the independent-gate bias and work-function engineering techniques. With the multi-Vth latches, the total active mode power consumption, the clock power, and the average leakage power are reduced by up to 50.3%, 22%, and 47%, respectively, while maintaining similar speed and data stability as compared to the standard single-Vth circuits. Furthermore, the area is reduced by up to 21% with the multi-Vth latches as compared to the circuits with single-Vth tied-gate transistors in a 32nm FinFET technology.