The paper has provided the proof-of-concept of using an Altera FPGA device and a NIOS II processor to implement the reduction of the phase noises and jitters on different clock sources with the Clock Cleaner. From the results, the low-cost Clock Cleaner has managed to significantly reduce the phase noise, random jitter and total jitter in the input clock sources from the Equipment A. In addition, the Clock Cleaner, has also exhibited jitter and phase noise characteristics that are comparable to the expensive clean clock generation sources (Equipment B). Equipment A + Clock Cleaner costs approximately $33k while Equipment B costs approximately $60k with comparable phase noise and jitter performance. The Clock Cleaner is a cost-effective clean clock source alternative that supports a wide range of reference clock frequencies. Since the Clock Cleaner is a separate unit, it can be connected to any low-cost signal generator to provide a clean clock source.