A Power Efficient Digitally Programmable Delay Element for Low Power VLSI Applications

Sekedi Bomeh Kobenge and Huazhong Yang
NICS, Department of Electronic Engineering, Tsinghua University, Beijing, P.R.C


In this paper, a low power digitally programmable delay element (DPDE) with monotonic delay characteristics is proposed. A dynamic current mirror controlled by the input and output signals is used to achieve a current-on-demand operation. To avoid direct currents the gates of the output inverter transistors are separately controlled. The static power is completely eliminated while dynamic power is significantly reduced to only 36uW when the unit is operating at 450MHz.