Memory-Aware Power Modeling for PAC DSP Core

Chen-Wei Hsu1,  Jia-Lu Liao1,  Jen-Chieh Yeh2,  Ji-Jan Chen2,  Shi-Yu Huang1,  Jing-Jia Liou1
1National Tsing Hua University, Taiwan, 2SoC Technology Center, Industrial Technology Research Institute, Taiwan


In this work, we propose a fast and accurate system-level power estimation methodology. To achieve high accuracy for an in-house digital signal processor, called PAC, we incorporate a hybrid power modeling scheme integrating three different levels of power models (including the instruction-level power model, the memory power model, and the transaction-based power model). These models are built using gate-level simulation first before being applied to the ESL simulation in which SystemC and instruction-set simulator (ISS) can be used to quickly perform the system-level power simulation with some realistic application programs. Within this system-level power modeling and simulation framework, one is able to analyze how memory configuration (e.g., cache sizes) will affect the system’s power consumption at a very early design stage.