In this paper, a low power and high speed reconfigurable resolution (adaptive) two step flash ADC is proposed. The proposed ADC enables exponential power reduction while the reduction in resolution is linear. In the proposed design unused parallel voltage comparators are switched to standby mode leading to consumption of only the leakage power. The proposed ADC design is compared with conventional 6-bit flash ADC designed is capable of operating over the input frequency range of 0.5 to 1GSPS at 8-bit, 10-bit, and 12-bit precision which has DNL< ±0.4LSB, INL< ±0.35LSB, SNR of 68.5dB and SNDR of 66.77dB for 12-bit operation. The proposed design has a peak power consumption of 8mW at 8-bit and 12mW at 12-bit 16mw, verified for post layout simulations in standard CMOS 65nm technology.