The process of scaling in silicon transistor has consistently resulted in smaller device geometry, higher device density and better performance. In conventional MOSFETs, control of Ioff for scaled devices requires very thin gate dielectrics and high doping concentrations. The industry roadmap predicts the barriers of continuous scaling will be due to physical limitations as well as practical technology. As the downscale of CMOS technology approaches physical limitations, the need arises for alternative device structures. Thus, this paper intends to study the effect of various gate lengths on the NMOS electrical characteristic by means of simulation study.