In this study, an experimental validated three-dimensional "atomistic" coupled device-circuit simulation approach is advanced to investigate the process-variation-effect (PVE) and random dopant fluctuation (RDF) induced characteristic fluctuations in planar metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) from 65-nm to 16-nm gate length. The RDF dominates the fluctuation of static noise margin (SNM). As the gate length of the planar MOSFETs scales from 65 nm to 16 nm, the normalized RDF-induced SNM fluctuation increases from 4% to 80%. To reduce the device variability induced fluctuation in circuit, a device with vertical-doping-profile and raised Vth is employed. The SNM is three times larger than the original 16-nm-gate SRAM. Moreover, the normalized RDF-induced SNM fluctuation is reduced by a factor of 2.67. Additionally, a 16-nm-gate silicon-on-insulator fin-type field-effect-transistor is used to further improve the SNM of SRAM. Due to the superior electrostatic integrity and larger effective device width than planar MOSFETs, the SNM of 16-nm-gate FinFET SRAM is six times larger than the original 16 nm SRAM with five times smaller SNM fluctuation. The study investigates the roll-off characteristics of SNM and provides an insight into design of fluctuation resistant nanoscale SRAM.