Comparative Analysis of Process Variation Impact on Flip-Flops Soft Error Rate

Hassan Mostafa,  Mohab Anis,  Mohamed Elmasry
University of Waterloo


Due to CMOS technology scaling, devices are getting smaller, faster, and operating at lower supply voltages. The reduced capacitance and power supply voltage and the increased chip density to perform more functionality result in increasing the soft errors and making them one of the essential design constraints at the same level as delay and power. Even though the impact of process variations on the performance and the power consumption has been investigated by many researchers, its impact on soft errors has not been paid enough attention. This impact is investigated in this work for 65-nm CMOS technology. The soft error yield is defined in this paper similar to the timing yield and the power yield. This paper shows that the soft error yield of the sense-amplifier based flip flop is very poor. Therefore, soft error mitigation techniques are required when using this flip-flop topology. The semi-dynamic flip-flop exhibits the best soft error yield behavior with a very high performance at the expense of large power requirement. Finally, some design insights are proposed.