ASQED 2015: Program, Rev. 5

SESSION 1A

Wednesday, Aug. 5, 2015

9:00AM-10:30AM Japan Room

Low Power Design and Interconnect Techniques

Chair: Yiran Chen, University of Pittsburgh

9:00AM
1A.1
Combined SRAM Read/Write Assist Techniques for Near/Sub-Threshold Voltage Operation
Farah Yahya¹, Harsh Patel¹, Benton Calhoun¹, Vikas Chandra²
¹University of Virginia, Charlottesville, ²ARM Inc.

9:15AM
1A.2
Energy Efficient Sub/Near-Threshold Ripple-Carry Adder in Standard 65 nm CMOS
Ali Asghar Vatanjou, Trond Ytterdal, Snorre Aunet
NTNU

9:30AM
1A.3
An Efficient Mesh-of-Tree Based Interconnect Architecture for High Performance 3D FPGAs
Vinod PANGRACIOUS¹, Zied MARRAKCHI², Habib MEHREZ²
¹American University in Dubai, ²UPMC Paris VI

9:45AM
1A.4
Current-Mode Simultaneous Bidirectional Transceiver for On-Chip Global Interconnects
Nijwm Wary and Pradip Mandal
Indian Institute of Technology, Kharagpur, India

SESSION 1B

Wednesday, Aug. 5, 2015

9:00AM-10:30AM USA Room

Error Prevention and Design for Robustness

Chair: Chen-Yong Cher, IBM

9:00AM
1B.1
SER mitigation techniques through selective flip-flop replacement
Pavan Vithal Torvi¹, Devanathan V. R.¹, Ashish Vanjari¹, Kamakoti V²
¹Texas Instruments, ²IITM

9:15AM
1B.2
Architectural Error Prediction using Probabilistic Error Masking Matrices
Zheng Wang¹, Hui Xie², Saumitra Chafekar², Sai Rama Usha A³, Anupam Chattopadhyay⁴
¹RWTH-Aachen University, ²RWTH-Aachen Univeristy, ³National Institute of Technology, ⁴Nanyang Technological University

9:30AM
1B.3
A Pipelined CORDIC Architecture and Its Implementation in All-Digital FM Modulator-Demodulator
Trio Adiono, Nur Ahmadi, Antonius P. Renardy, Ashbir A. Fadila, Naufal Shidqi
School of Electrical Engineering and Informatics, Bandung Institute of Technology

9:45AM
1B.4
Automatic Register Balancing in Model-based High-level Synthesis
Chandan Karfa
Synopsys

10:00AM
1B.5
SynDFG: Synthetic Dataflow Graph Generator for High-level Synthesis
Sharad Sinha and Wei Zhang
The Hong Kong University of Science and Technology

10:15AM
1B.6
Design for Reliability: A Novel Counter Matrix Code for FPGA based Quality Applications
Ahilan Appathurai¹ and Deepa P²
¹Research Scholar, ²Professor

SESSION 2A

Wednesday, Aug. 5, 2015

11:00AM-12:00PM Japan Room

Testing and Packaging

Chair: Yiran Chen, University of Pittsburgh

11:00AM
2A.1
Optimizing Test Time for Core-Based 3-D Integrated Circuits by Genetic Algorithm
Tanusree Kaibartta¹, Chandan Giri², Hafizur Rahaman², Debesh K. Das³
¹ISM Dhanbad, ²Indian Institute of Engineering Science and Technology, Shibpur, ³Jadavpur University

11:15AM
2A.2
Method to Improve Ball Grid Array Imax Distribution for Small Form Factor Package Design
Chin Lee Kuan, Jimmy Huang, Bok Eng Cheah, Jackson Kong
Intel Microelectronics (M) Sdn. Bhd

11:30AM
2A.3
MIM Capacitance Efficiency Study for High Speed I/O Power Integrity Network Design: MIM and MIMless High Speed I/O Performance Characterization
Fern Nee Tan, Ming Dak Chai, Mohamad Shahrir Tamrin
Intel Microelectronics

11:45AM
2A.4
Detection of Intermittent Resistive Faults in Electronic Systems Based on the Mixed-Signal Boundary-Scan Standard
Hans G. Kerkhoff and Hassan Ebrahimi
University of Twente

SESSION 2B

Wednesday, Aug. 5, 2015

11:00AM-12:00PM USA Room

RF Design and EMC

Chair: Chen-Yong Cher, IBM

11:00AM
2B.1
True 3D Antenna for UHF RFID Application
Yongsheng Zhang, Jun Sun, Bin Wang
Hangzhou University of Electronic Science and Technology

11:15AM
2B.2
Electromigration Failure Mechanism Comparison Between Wafer Level and Package Level Reliability Test on Via Structure
Dulin Wang, Cheng Nee Ong, Hong Seng Ng
X-FAB Sarawak Sdn. Bhd.

11:30AM
2B.3
Radio-Frequency Silicon-based CMOS-Compatible MEMS Variable Solenoid Micro-Fluidic Inductor with Galinstan-Based Continuously-Adjustable Turn-Ratio Technique
Fatemeh Banitorfian, Farshad Eshghabadi, Asrulnizam Abd Manaf, Norlaili Mohd Noh, Mohd Tafir Mustaffa
Advanced Integrated System Device Group (AISDe), School of Electrical and Electronic Engineering, Universiti Sains Malaysia (USM), Nibong Tebal, Malaysia

SESSION 3A

Wednesday, Aug. 5, 2015

1:30PM-3:00PM Japan Room

Clock Network Design and Routing

Chair: Fakhrul Zaman Rokhani, University Putra Malaysia

1:30PM
3A.1
Clock Gating Assertion Check: An Approach towards Achieving Faster Verification Closure on Clock Gating Functionality
Jian Zhong Wang¹, Bakhtiar Affendi Rosdi², Norlaili Mohd Noh²
¹Intel Corporation, ²Universiti Sains Malaysia

1:45PM
3A.2
An All-Digital Adaptive Approach to Combat Aging Effects in Clock Networks
Senthil Arasu, Mehrdad Nourani, Hao Luo
University of Texas at Dallas

2:00PM
3A.3
An Efficient Buffer Sizing Algorithm for Clock Trees Considering Process Variations
Chao Deng, Yici Cai, Qiang Zhou, Zhuwei Chen
Tsinghua University

2:15PM
3A.4
3-D Global Routing with Layer Directive and Scenic Constraints
Zhongdong Qi, Yici Cai, Qiang Zhou, Zhuwei Chen
Tsinghua University

2:30PM
3A.5
An Accurate Detailed Routing Routability Prediction Model in Placement
Quan Zhou, Xueyan Wang, Zhongdong Qi, Zhuwei Chen, Qiang Zhou, Yici Cai
Tsinghua University

SESSION 3B

Wednesday, Aug. 5, 2015

1:30PM-3:00PM USA Room

Emerging Technologis and Applications

Chair: Fatimah Khairiah Bt Abd Hamid, Ascend Microsystems

1:30PM
3B.1
Performance Analysis of 22 nm Deep Submicron NMOS Transistors
Kim Ho Yeap¹, Jor Gie Liew¹, Siu Hong Loh¹, Humaira Nisar¹, Zairi Ismael Rizman²
¹Tunku Abdul Rahman University, ²MARA University of Technology

1:45PM
3B.2
Testing Power-Delivery TSVs
Shi-Yu Huang¹, Hua-Xuan Li¹, Hua-Cheng Fu¹, Jin-Cheng Jiang¹, Ding-Ming Kwai dm², Yung-Fa Chou²
¹National Tsing Hua Univ.,, ²ICL, Industrial Technology Research Institute

2:00PM
3B.3
Cluster Error Correction and On-Line Repair for Real-Time TSV Array
Tsung-Chu Huang
National Changhua University of Education, Taiwan

2:15PM
3B.4
Decision-based Biochips: A Novel Design for Concurrent Execution of Networked Bioassays integrated in Scalable DMFBs
Pranab Roy¹, Mriganka Chakraborty¹, Aatreyi Bal¹, Hafizur Rahaman¹, Parthasarathi Dasgupta²
¹Indian Institute of Engineering Science and Technology,Shibpur,India, ²Indian Institute of Management Calcutta,India

2:30PM
3B.5
Compact FPGA Implementation of PRESENT with Boolean S-Box
Jia Jun Tay¹, Mou Ling Dennis Wong¹, Ming Ming Wong¹, Cishen Zhang², Ismat Hijazin²
¹Swinburne University of Technology Sarawak Campus, ²Swinburne University of Technology

2:45PM
3B.6
Realization of Non-linear i-v Curve with Low Power Dissipation Using Linear Ion Drift Memristor Model
Anusudha T A and Prabaharan SRS
School of Electronics Engineering, VIT University Chennai campus, Chennai

SESSION 4A

Wednesday, Aug. 5, 2015

3:30PM-4:45PM Japan Room

Special Chip Fabraticaion Technology and design

Chair: Norhayati Bt Soin, Universiti Malaya

3:30PM
4A.1
High Voltage MOS Modeling with BSIM4 Sub-Circuit Model
Chiew Ching Tan and Philip Beow Yew Tan
Silterra Malaysia Sdn. Bhd

3:45PM
4A.2
A New 600V Partial SOI LDMOS with Step-doped Drift Region
Yue Hu¹, Hao Wang², Caixia Du², Yuzhun Du², Peigang Deng², Jin He², Lei Song³, Haiqin Zhou⁴, Yong Wu⁴
¹Peking University Shenzhen SOC Key Laboratory, PKU-HKUST Shenzhen-Hongkong Instiutuitions, Peking University Shenzhen Institute, P. R. China, ²Shenzhen SOC Key Laboratory, ³Shenzhen SuperD Co. Ltd., ⁴TIANMA MICRO-ELECTRONICS.CO.,LTD

4:00PM
4A.3
A Field-Based Parasitic Capacitance Model with 3-D Terminal and Terminal Fringe Components
Aixi Zhang¹, Wei Zhao¹, Yue Hu¹, Jin He¹, Qingxing He¹, Lei Song², Haiqin Zhou³, Yong Wu³
¹Peking University Shenzhen SOC Key Laboratory, ²Shenzhen SuperD Co. Ltd.,, ³TIANMA MICRO-ELECTRONICS.CO.,LTD,

4:15PM
4A.4
Non-Linearity Analysis of Stochastic Time-to-Digital Converter
Val Mikos¹, Toru Nakura², Kunihiro Asada²
¹ETH Zurich & University of Tokyo, ²University of Tokyo

4:30PM
4A.5
Fully-Hybrid Computer-Aided RF LNA Design and Evaluation for GSM-1900 Standard Band
Farshad Eshghabadi, Fatemeh Banitorfian, Norlaili Mohd Noh, Mohd Tafir Mustaffa, Asrulnizam Abd Manaf
AISDe, Universiti Sains Malaysia

SESSION 4B

Wednesday, Aug. 5, 2015

3:30PM-4:45PM USA Room

Bio-chip and Integrated Systems

Chair: Asral B. Bahari Jambek, Universiti Malaysia Perlis

3:30PM
4B.1
A Wide Input Voltage Range Start-up Circuit for Solar Energy Harvesting System
Shourya Kansal¹, Ajay Mantha², Priyamvada Y.B.¹, Gajendranath Chowdary³, Shiv Govindh Singh¹, Ashudeb Dutta¹
¹Indian Institute of Technology Hyderabad, ²Redpine Signals Inc., ³Indian Institute of Technology Delhi

3:45PM
4B.2
On Enhancing the Reliability of Digital Microfluidic Biochips (DMFB) through Electrode Cells Health Classification
Madiha Arshad Sheikh, Noohul Basheer Zain Ali, Nor Hisham Hamid, Fawnizu Azmadi Hussin, Vineeta Shukla
UTP

4:00PM
4B.3
Resonant Power Supply Noise Cancelling with Noise Detector based in DLL and Vernier TDC
Masahiro Kano, Toru Nakura, Kunihiro Asada
The University of Tokyo

4:15PM
4B.4
An on-chip Transfer Function Measurement of PLLs with Triangular Modulated Stimulus
Toshiyuki Kikkawa, Toru Nakura, Kunihiro Asada
The University of Tokyo

4:30PM
4B.5
PrimeTime Web-based Report Analyzer (PTWRA) Tool
Fawaz Mohammed¹, Fakhrul Zaman Rokhani¹, Sreedharan Baskara Daas², Roslina Mohd Sidek¹
¹University Putra Malaysia, ²Intelligent Circuits Engineering