As VLSI technology continuously scales down, robust clock tree synthesis (CTS) has become increasingly critical in an attempt to generate a high-performance synchronous chip design. Clock skew resulted by process variation can be significantly different from the nominal value. In this paper, we propose an efficient buffer sizing algorithm to solve the skew optimization problem in presence of process variations. By analyzing the influence of process variations on wire delay and buffer delay, we make a quantitative estimation of the skew distribution under Monte-Carlo SPICE simulations. The number and size of buffers on some critical paths are rearranged to reduce the skew results under process variations. Experiment results which are evaluated on ISPD 2010 benchmarks show that our algorithm achieves a significant 71% reduction on worst local skew and a 2% reduction on power consumption.