Time-to-Digital Converter (TDC) are employed to transform information given by the time difference of two signal events into the digital domain. There are multiple possible architectures, yet the stochastic TDC excels in high resolution at narrow dynamic ranges. Since the transfer function relies on process, voltage and temperature (PVT) variation, this unfortunately results in a non-linear transfer function. The goal hence becomes to quantify and derive the non-linearity and use the implications thereof to steer the design to favorable results by minimizing non-linearity issues. This paper derives the non-linearity characteristics of the stochastic TDC by first demonstrating the working principle, followed by the derivation of the non-linear aspects. Moreover, the implications thereof, such as the optimal dynamic range and effective resolution are presented. Additionally, an example of how the theoretical findings can influence circuit design to reach minimum non-linearity errors is demonstrated. In support of the derived theory, a 4-bit stochastic TDC in standard 180nm CMOS technology is designed. Using Monte Carlo simulation, the theoretical findings are evaluated against the circuit simulation, as well as against an ideal software model.