Wafer level reliability (WLR) and package level reliability (PLR) test methods are widely used for Eectromigration (EM) accelerated lifetime test. These two methods on different EM via structures are carried out in this paper and the experimental result shows single via terminated EM structure lifetime is comparable between WLR and PLR methods while stack via terminated EM structure lifetime is not coincident based on Black’s equation. Physical failure analysis is done on the two structures and the different failure mechanisms between WLR and PLR methods on stack via terminated structure are found. The explanation is also discussed to the failure mechanism.