High Voltage MOS Modeling with BSIM4 Sub-Circuit Model

Chiew Ching Tan and Philip Beow Yew Tan
Silterra Malaysia Sdn. Bhd


This paper presents a technique for modeling high-voltage MOS (HVMOS) devices with BSIM4 sub-circuit model. Two voltage-dependent resistors, rd and rs are added into the drain and source side of a core BSIM4 model to capture the high voltage effects; quasi-saturation (QS) and self-heating effect (SHE). We use rd to capture QS. The voltage drop across rd captures the actual physical effect that causes QS. To model SHE, we use an empirical method. Rs is used to ensure the effective drain-to-source voltage (Vds_eff) and effective gate-to-source voltage (Vgs_eff) drop about the same amount. Hence, the saturation point remained unchanged. When Vds further increases after the saturation point, the Vd drop across rs is larger, hence more Id reduces. This causes an effect similar to SHE. By applying the proposed methodology, we able to fit to the silicon data. We also discuss the methodology to model the SHE dynamic effect by introducing a capacitor (cs) in parallel with rs. When Vd pulse is applied at the Vd, cs is being charged and almost no current flowing thru rs. Hence, no SHE at that time. When cs is fully charged, then rs takes effect. This captures the dynamic characteristics of SHE.