SER mitigation techniques through selective flip-flop replacement

Pavan Vithal Torvi1,  Devanathan V. R.1,  Ashish Vanjari1,  Kamakoti V2
1Texas Instruments, 2IITM


The advancement in the semiconductor manufacturing process has reduced the device dimensions, which in turn has reduced design and manufacturing costs of the Integrated Chips (IC). This has accelerated the IC penetration in automobiles, health care and safety critical systems. However, the smaller device dimensions have made the IC¿s vulnerable to soft-errors. The sequential cells contribute significantly to the soft-error rate (SER) of a given design. Some of the soft-errors get masked and do not cause any adverse impact. The masking can occur due to logic or timing reasons. This paper presents a flow that uses the Timing Vulnerability Factor (TVF) and Architecture Vulnerability Factor (AVF) of the sequential instances in a given design to reduce its soft-error rate (SER). The paper proposes a novel method to efficiently compute the TVF and AVF parameters followed by a linear programming technique that uses these parameters to reduce the SER of the given design. Using the proposed technique, we have reduced the sequential cell contribution to the SER of an IP in an inhouse design by 36% for an increase of 9% in sequential cells area.