Optimizing Test Time for Core-Based 3-D Integrated Circuits by Genetic Algorithm

Tanusree Kaibartta1,  Chandan Giri2,  Hafizur Rahaman2,  Debesh K. Das3
1ISM Dhanbad, 2Indian Institute of Engineering Science and Technology, Shibpur, 3Jadavpur University


System-on-a-chip (SOC) uses embedded cores those require a test access architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. This approach can be used for testing of three dimensional stacked integrated circuits (SICs) based on through silicon vias (TSVs). Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D stacked ICs implemented using Through-Silicon Vias (TSVs) technology and present genetic algorithm for minimizing the post bond test time for 3D SICs under the constraints on the number of TSVs and the available TAM width. Given a TAM width available to test a system-on-achip, our algorithm partitions this width into different groups and places the cores of these groups in different layers in 3D design with the goal to optimize the total test time. The experimental results establish the effectiveness of our algorithm