Circuit aging due to Bias Temperature Instability (BTI) has become one of the major reliability concerns in digital integrated circuits. In this paper, we analyze the impact of asymmetrical aging due to BTI in the clock tree segments of power efficient designs. The non-uniform aging of launch and capture clock segments not only could violate the setup timing but also could result in gross hold violations. Aging in clock networks also results in pulse width compression which impacts the half-cycle paths’ timing adversely. We present an All-Digital technique to detect the aging effects and measure quantitatively the extent of pulse-width-distortion. We also present a method to use the measurement results to correct the pulse width distortion such that the clock network is restored to a 50-50 duty cycle. The technique is validated using SPICE simulation based on 45nm industry standard library.