This paper investigates the use of combined read and write assist techniques to reduce the minimum operating voltage (VMIN) of the 6T SRAM bit-cell. While write failures initially limit VMIN, applying write assist introduces row and column half-select failures. Thus, read and write assist must be combined to allow scaling VMIN down to near/sub threshold voltages. We find that combining negative bitline (BL) for write assist with array VDD boosting for read assist is most effective for reducing the array VMIN and eliminating half-select failures for commercial 130nm and sub-20nm FinFET technologies across different process corners and temperatures. The proposed combination results in the highest reduction in SRAM VMIN (to 300mV for FinFET and to 600mV for 130nm CMOS). This paper also shows that controlling the degree of applied assist based on the chip corner will allow further reductions in VMIN for the 130nm CMOS (to 450mV) and the required assist needed to achieve VMIN for both the FinFET and the 130nm bit-cells.