ASQED 2010 Program
SESSION 1A
Tuesday August 3, 2010
1:30PM-3:30PM
Sensors and Imaging
Chair: Ateet Bhalla
Co-Chair: Tanay Karnik, Intel
1:30PM
1A.1
Integrated Memristor CMOS Image Sensor for the future Image Recognition Systems (INVITED)
Kyoungrok Cho
Chungbuk National University
2:00PM
1A.2
A 0.18μm CMOS Shock Wave Generator with an On-chip Antenna and a Digitally Programmable Time Delay Circuit
KHANH Nguyen, Masahiro SASAKI, Kunihiro ASADA, Taihei MONMA
The University of Tokyo, Japan
2:20PM
1A.3
FPGA implementation of Compressive Sampling for Sensor Network Applications
Yan Wang1, Amine Bermak1, Farid Boussaid2
1Hong Kong University of Science and Technology, 2University of Western Australia
2:40PM
1A.4
Block-Based Compressive Sampling for Digital Pixel Sensor Array
Milin Zhang, Yan Wang, Amine Bermak
Hong Kong University of Science and Technology
3:10PM
1A.5
Gate Driver Circuit Design Optimization for TFT-LCD Panel Manufacturing
Kuo-Fu Lee1, Yiming Li1, I-Hsiu Lo1, Tony Chiang2, Kuen-Yu Huang2, Tsau-Hua Hsieh2
1Department of Electrical Engineering, National Chiao Tung University, 2Chimei-InnoLux Corporation
SESSION 1B
Tuesday August 3, 2010
1:30PM-3:30PM
Power Gating and Power Distribution Noise
Chair: Suphachai Sutanthavibul
Co-Chair: Yu Wang, Tsinghua University
1:30PM
1B.1
High-Speed and Low-Leakage MTCMOS Memory Registers
Hailong Jiao and Volkan Kursun
The Hong Kong University of Science and Technology
2:00PM
1B.2
PCH Power Gating Domains Implementation and Design Challenges
CHEE KONG UNG, SEAN CHAN, LEE KEE YONG, JESS CHENG SING KIU
Intel Microelectronic
2:20PM
1B.3
A Toggle-Type Peak Hold Circuit for Local Power Supply Noise Detection
Yuki Tamaki1, Toru Nakura2, Makoto Ikeda1, Kunihiro Asada1
1Dept. of Electronic Engineering and Information Systems, The University of Tokyo, 2VLSI Design and Education Center, The University of Tokyo
2:40PM
1B.4
Dynamic Forward Body Bias Enhanced Tri-Mode MTCMOS
Hailong Jiao and Volkan Kursun
The Hong Kong University of Science and Technology
3:10PM
1B.5
Power Density Aware Power Gate Placement Optimization Scheme
Lee Kee Yong and Chee Kong Ung
Intel Inc.
SESSION 1C
Tuesday August 3, 2010
1:30PM-3:00PM
Micro Electro-Mechanical Systems
Chair: Farhang Yazdani
Co-Chair: TBD
1:30PM
1C.1
Temperature Dependent Actuation Voltage for Longer MEMS Switch Lifetime
Chean Hung Lai and Wallace S.H Wong
Swinburne University of Technology (Sarawak Campus)
2:00PM
1C.2
Experimental Considerations for Fabrication of RF MEMS Switches
Hamood Ur Rahman and Rodica Ramer
University of New South Wales (UNSW), Sydney, Australia
2:40PM
1C.4
A Review of Papers on Architecture and Operation of Micro-thermophotovoltaic System for MEMS Power Generation
Othman Sidek, Mohammad Zulfikar Ishak, Jalal Abd. Aziz, Muhamad Azman Miskam
Universiti Sains Malaysia
3:10PM
1C.5
Dry Etching Process Using XeF2 on Microhotplate Device
Zaini Abdul Halim1 and Zarina Tardan2
1CEDEC, USM, 2PPKEE, USM
SESSION 1P
Tuesday August 3, 2010
1:30PM-4:00PM
Poster Papers
Chair: Volkan Kursun, Hong Kong University of Science and Technology
Co-Chair: TBD
1:30PM
1P.1
Process Variation Study of Ground Plane SOI MOSFET
Mehdi Saremi1, Behzad Ebrahimi1, Ali Afzali-Kusha1, Mohammad Saremi2
1School of Electrical and Computer Engineering of University of Tehran, 2Azad University of Khorram Abad
1:30PM
1P.2
Thermal Analysis of High Power LEDs at Different Drive-In Current
WEI-CHING LIEW, MUTHARASU DEVARAJAN, CHAO-YUI ONG
University Science Malaysia
1:30PM
1P.3
The Influence of Still Air Environment on Thermal Transient Measurement of High Power LED
Anithambigai Permal, Teeba Nadarajah, Dinash Kandasamy, Mutharasu Devarajan
Universiti Sains Malaysia
1:30PM
1P.4
Variable Gain CMOS Potentiostat for Dissolved Oxygen Sensor
Mei Yee Ng and Yuzman Yusoff
MIMOS
1:30PM
1P.5
Package Level Failure Analysis: New Techniques and New Instruments for Better Results
Simona Pappalardo1, Davide Caccialanza1, Zukhairi Md Sarip2
1St Microelectronics, Agrate Brianza (Italy), 2St Microelectronics, Muar (Johor, Malaysia)
1:30PM
1P.6
A Model for Transient Fault Propagation Considering Glitch Amplitude and Rise-Fall Time Mismatch
farshad firouzi1, saman kiamehr1, Poya monshizadeh1, Mohammad Saremi2, Ali Afzali-Kusha1, Sied Mehdi Fakhraie1
1university of tehran, 2Azad University of Khorram Abad
1:30PM
1P.7
Design of a Contactless Sensor System for Woven-Bag Manufacture Monitoring
Montri Supattatham, Narongrit Waraporn, Weerasak Thumbanthu, Jonathan H. Chan
School of Information Technology, King Mongkut’s University of Technology Thonburi
1:30PM
1P.8
A Lower-Band UWB LNA with Integrated 7kV/15kV ESD Protection
He Tang1, Bo Qin2, Xin Wang3, Siqiang Fan1, Lin Lin1, Albert Wang1, Jun He4
1University of California, 2Tsinghua University, 3Freescale Semiconductor, 4GSMC
1:30PM
1P.9
Mixed AC/DC-Coupled Averaging Technique for ADC Nonlinearity Reduction
Siqiang Fan1, He Tang2, Hui Zhao2, Albert Wang2, Bin Zhao1, Xin Wang2
1Freescale Semiconductor, 2University of California
SESSION 2A
Tuesday August 3, 2010
4:00PM-6:00PM
Advances in Analog & RF IC Design and Modeling
Chair: Farhang Yazdani
Co-Chair: Volkan Kursun, Hong Kong University of Science and Technology
4:00PM
2A.1
A Nonlinear S-parameters Behavioral Model for RF LNAs
Tamer Riad and Qi Jing
Mentor Graphics Corporation
4:30PM
2A.2
Characterizing PLL Jitter from Power Supply Fluctuation Using Mixed-Signal Simulations
Qi Jing, Tamer Riad, See-Mei Chan
Mentor Graphics Corp.
5:00PM
2A.3
Design and Measurement of Band V WCDMA LNA Utilizing Design Kit with Scalable Parametric Cell Inductors
Syahrizal Salleh and Mohamad Faizal Hashim
TM R&D
5:20PM
2A.4
Functional ECO Automation Challenges and Solutions
Andal Jayalakshmi and Ganapathy Ramalingam
intel Corporation
5:40PM
2A.5
A Low-Noise Phase-Locked Loop with Programmable Gain VCO
Lip Kai Soh
Altera Corporation
SESSION 2B
Tuesday August 3, 2010
4:00PM-6:00PM
Automation Algorithms and VLSI Architectures
Chair: Kyoungrok Cho
Co-Chair: Young Hwan Kim
4:00PM
2B.1
Throughput-Driven Hierarchical Placement for Two-Dimensional Regular Multicycle Communication Architecture
Ya-Shih Huang and Juinn-Dar Huang
National Chiao Tung University
4:30PM
2B.2
Adaptive Hardware Context-Switching Approach for Reconfigurable Systems
Trong-Yen Lee, Shiau-Jiun Tseng, Che-Cheng Hu
National Taipei University of Technology
5:00PM
2B.3
A Novel VLSI Architecture for Walsh-Hadamard Transform
Sudip Ghosh, Somsubhra Talapatra, Santi P Maity, Hafizur Rahaman
Bengal Engineering and Science University-Shibpur
5:20PM
2B.4
Extended Compatibility Path Based Hardware Binding Algorithm for Area-Time Efficient Designs
Udit Dhawan, Sharad Sinha, Siew-Kei Lam, Thambipillai Srikanthan
Nanyang Technological University
5:40PM
2B.5
Locality Considerations In Exploring Custom Instruction Selection Algorithms
Amir Yazdanbakhsh, Mostafa E. Salehi, Saeed Safari, Sied Mehdi Fakhraie
University of Tehran
SESSION 2C
Tuesday August 3, 2010
4:00PM-6:00PM
Advances in Design Verification
Chair: Chin Hai Ang, Altera Corporation (M) Sdn Bhd, Malaysia
Co-Chair: Sudarshan Bahukudumbi, Intel Corporation, Malaysia
4:00PM
2C.1
Enhanced on-Die RC Characterization Methodology
Fern Nee Tan and Li Chuang Quek
Intel Microelectronics
4:30PM
2C.2
Performance Modeling Based on Core/Cache Design Validation Results for Predictive Analysis
Sze Ming Chow and Al Vin Tan
Intel Corporation, Penang, Malaysia
5:00PM
2C.3
Design Aware Scheduling of Dynamic Testbench Controlled Design Element Accesses in FPGA-based HW/SW Co-simulation Systems for Fast Functional Verification
Somnath Banerjee and Tushar Gupta
Mentor Graphics Pvt. Ltd.
5:20PM
2C.4
Constraint Sequence Solving for VLSI Design
Ateet Bhalla
Technocrats Institute of Technology
5:40PM
2C.5
A Systems Approach to Verification using Hardware Acceleration
Sharad Kumar, Sainath Shanbhag, Gaurav Verma, Mohit Mongia
Freescale Semiconductor
SESSION 3A
Tuesday August 3, 2010
4:00PM-6:00PM
Biochips and Biomedical Circuits
Chair: Yu Wang, Tsinghua University
Co-Chair: Yiran Chen
4:00PM
3A.1
A new CMOS/Microfluidic interface for Cells manipulation and separation in LoC devices (INVITED)
Mohamed Amine Miled and Mohamad Sawan
Ecole Polytechnique de Montreal
5:00PM
3A.2
Towards Fault-Tolerant and Reconfigurable Digital Microfluidic Biochips (INVITED)
Krishnendu Chakrabarty and Yang Zhao
Duke University
SESSION 4A
Wednesday August 4, 2010
1:30PM-3:30PM
Bio-sensing and Bio-system Design
Chair: Krishnendu Chakrabarty
Co-Chair: Wei Zhang, Nanyang Technological University
1:30PM
4A.1
A 1.2-V Reconfigurable Resolution CMOS Image Sensor with Energy Harvesting Capability (INVITED)
Amine Bermak and Chao Shi
Hong Kong University of Science and Technology
2:00PM
4A.2
Membrane Protein Biosensor Arrays on CMOS (INVITED)
Andrew Mason and Yue Huang
Michigan State University
2:30PM
4A.3
Hardware Computing for Brain Network Analysis (INVITED)
Yu Wang1, Yong He2, Yi Shan1, Tianji Wu1, Di Wu1, Huazhong Yang1
1Tsinghua Univ., 2Beijing Normal Univ.
2:50PM
4A.4
Signal Processing Electronics in Bio-implantable Systems: Design Challenges and Emerging Solutions (INVITED)
Seetharam Narasimhan1, Jongsun Park2, Swarup Bhunia1
1Case Western Reserve University, 2Korea University
3:10PM
4A.5
The Application of Spintronic Devices in Magnetic Bio-sensing (INVITED)
Yiran Chen1, Xiaobin Wang1, Zhenyu Sun2, Hai Li2
1Seagate Technology, 2Polytechnic Institute of New York University
SESSION 4B
Wednesday August 4, 2010
1:30PM-3:30PM
Reliability Enhancement Techniques and Modeling of Process Variations
Chair: Young Hwan Kim
Co-Chair: Lee Kee Yong
1:30PM
4B.1
Optimizing Device Size for Soft Error Resilience in Sub-Micron Logic Circuits
Warin Sootkaneung and Kewal K. Saluja
Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI, 53706, USA
2:00PM
4B.2
Statistical Leakage Estimation for DRAM Circuits
Hyungwoo Lee1, Heejung So2, Seungho Jung2, Chanseok Hwang2, Jongbae Lee2, Moonhyun Yoo2
1Computer-Aided Engineering Team, Semiconductor R&D Center, Samsung Electronics Co., Ltd, 2
2:30PM
4B.3
Spatial Correlation Extraction with a Limited Amount of Measurement Data
Shu-Han Whi, Bing-Shiun Su, Yu-Min Lee, Chi-Wen Pan
National Chiao Tung University
2:50PM
4B.4
Peak Current Reduction Using an MTCMOS Technique
Tsung-Yi Wu1, Liang-Ying Lu2, Lih-Yih Chiou2, Jing-Wen Shi1
1National Changhua University of Education, 2National Cheng Kung University
3:10PM
4B.5
A New Block-Based SSTA Method Considering Within-die Variation
Saman Kiamehr, Amir Reza Ahmadi Mehr, Seyed Nima Mozaffari, Ali Afzali Kusha
University of Tehran
SESSION 4C
Wednesday August 4, 2010
1:30PM-3:30PM
Emerging Technologies and Noise Isolation Techniques
Chair: Farhang Yazdani
Co-Chair: Rohit Sharma
1:30PM
4C.1
A Complementary Single-Electron 4-bit Multiplexer
Thomas Tsiolakis1, Nikos Konofaos2, George Alexiou1
1University of Patras, 2University of the Aegean
2:00PM
4C.2
Crosstalk Analysis in Carbon Nanotube Interconnects and Its impact on Gate Oxide Reliability
Debaprasad Das and Hafizur Rahaman
School of VLSI Technology, Bengal Engineering and Science University, Shibpur, India.
2:30PM
4C.3
Active Filters for Harmonics Elimination in Solar Photovoltaic Grid-Connected and Stand-Alone Systems
Indranil Bhattacharya, Yuhang Deng, Simon Foo
Florida State University
2:50PM
4C.4
The Impact of Electromagnetic Coupling of Guard Ring Metal Lines on the Performance of On-chip Spiral Inductor in Silicon CMOS
Mohd Hafis Mohd Ali1, Chun-Lee Ler2, Subhash C. Rustagi2, Yusman M. Yusof2, Narain D. Arora2, Burhanuddin. Y. Majlis3
1Silterra Malaysia, Universiti Kebangsaan Malaysia, Bangi, Malaysia, 2Silterra Malaysia, 3Universiti Kebangsaan Malaysia, Bangi, Malaysia
3:10PM
4C.5
An Analog Optimal Waveform Design for UWB Communications
Ahmad Ghanaatian-Jahromi1, Adib Abrishamifar1, Ali Medi2, Abbas Akbarzadeh1
1Electrical Department, Iran University of Science and Technology, 2Electrical Department, Sharif University of Technology
SESSION 5A
Wednesday August 4, 2010
4:00PM-6:00PM
Design for Low Power and Reliability
Chair: Suphachai Sutanthavibul
Co-Chair: Lee Kee Yong
4:00PM
5A.1
A High Throughput, Metastability-Free GALS Channel Based on Pausible Clock Method
Mohammad Ali Rahimian, Siamak Mohammadi, Mohammad Fattah
Dependable Systems Design Lab, School of ECE, University of Tehran, Tehran, Iran
4:30PM
5A.2
A Case Study of Short Term Cell-Flipping Technique for Mitigating NBTI degradation on Cache
Yuji Kunitake1, Toshinori Sato2, Hiroto Yasuura1
1Kyushu University, 2Fukuoka University
5:00PM
5A.3
An Analysis of Fault Effects and Propagations in ZPU: The World's Smallest 32 bit CPU
Mahroo Zandrahimi, Hamid R. Zarandi, Alireza Rohani
Amirkabir University, Iran
5:20PM
5A.4
Effect of Gate-level Design Margin Relaxation on Overall Circuit Performance Metrics in VLSI design
Jae Hoon Kim and Young Hwan Kim
Postech
5:40PM
5A.5
A High Throughput Low Power Compact AES S-box Implementation using Composite Field Arithmetic and Algebraic Normal Form Representation
M. M. Wong and M. L. D Wong
Swinburne University of Technology (Sarawak Campus)
SESSION 5B
Wednesday August 4, 2010
4:00PM-6:00PM
IC Packaging and Power Delivery
Chair: Farhang Yazdani
Co-Chair: Ibrahim Bin Ahmad
4:00PM
5B.1
A Formal Approach toward Developing an Equivalent Circuit for High-Speed Coupled Interconnects with Intermediate Ground Insertion
Rohit Sharma and Kiyoung Choi
Seoul National University
4:30PM
5B.2
Wirebond Vs. Flip Chip Design of High Speed 3D Stacked Memory Packages
Farhang Yazdani
BroadPak Corporation
5:00PM
5B.3
A Study on the Electrical Properties of the Power Distribution Network using a Hybrid Domain Decomposition Method
Varvara Kollia1, Andreas Cangellaris2, Manuel Luschas1
1NetLogic Microsystems, 2University of Illinois at Urbana-Champaign
5:20PM
5B.4
Fast Transient Simulation Algorithm for a 3D Power Distribution Bus
Waqar Ahmad1, Rajeev Kumar Kanth2, Qiang Chen1, Li-Rong Zheng1, Hannu Tenhunen1
1KTH Royal Institute of Technology sweden, 2University of Turku Finland
5:40PM
5B.5
Efficient Reduction Technique of Resistive Mesh Structured Power Network
Jinwook Kim and Young Hwan Kim
POSTECH
SESSION 5C
Wednesday August 4, 2010
4:00PM-6:00PM
Semiconductor Technologies and Scaling Issues
Chair: Ateet Bhalla
Co-Chair: Rajiv Joshi, IBM
4:00PM
5C.1
Statistical Model for Subthreshold Current Considering Process Variations
Seyed Nima Mozaffari and Ali Afzali-Kusha
Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering University of Tehran
4:30PM
5C.2
Derivative Superposition Method for DG MOSFET Application to RF Mixer
Shuai Huang1, Xinnan Lin2, Yiqun Wei1, Jin He3
1The Key Laboratory of Integrated Microsystems, School of Computer & Information Engineering, Peking University Shenzhen Graduate School, Shenzhen 518055, P. R. China, 2Peking University Shenzhen SOC Key Laboratory, PKU HKUST Shenzhen Institute, W303, West Tower, IER Bldg., Hi-Tech Industrial Park South, Shenzhen 518057, P. R. China, 3TSRC, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871, P. R. China
5:00PM
5C.3
Nonlinear Mismatch Modeling of Resistor Device for Circuit Simulations
Muhamad Amri Ismail and Iskhandar Md Nasir
MIMOS Berhad
5:20PM
5C.4
Phase Change Memory and Paradigm Shift to In-System Programming
Darwin Wong, Clifford Smith, Poorna Kale
MICRON
5:40PM
5C.5
Effect of High Tensile Inter Layer Dielectric on Hook Shaped Idsat Characteristics of 0.13um CMOS Technology
Philip Beow Yew Tan, Chin Fui Chua, Subhash Chander Rustagi
Silterra Malaysia Sdn. Bhd.
