Performance Modeling Based on Core/Cache Design Validation Results for Predictive Analysis

Sze Ming Chow and Al Vin Tan

Intel Corporation, Penang, Malaysia

Abstract

The product development phase of a single processor design from inception till production is an extremely long process taking up to ~4 years per cycle. Along the way, numerous prediction tools have been utilized for pre-silicon performance prediction in order to forecast the yield, power & speed binning of the product. This information is critical for the necessary product/resource planning to be carried out. However, with the ever changing market trends, we can rarely predict with great accuracy the desired performance range or feature set which is currently in demand. Therefore, there is a dire need for a systematic and effective method of predictive analysis on post-silicon devices with regards to power, frequency, level and yield performance. Prediction based on post-silicon measured data are often more accurate (albeit heuristic) if compared to pre-silicon predictions. With the availability of a post-silicon based performance model, ad-hoc predictive analysis can be carried out for a variety of performance configurations without the need of actually having to carry out a full scale mass validation on the silicon.