CHEE KONG UNG, SEAN CHAN, LEE KEE YONG, JESS CHENG SING KIU
Intel Microelectronic
Power gating technique is crucial in controlling and reducing standby leakage current for SoC low power design. Its implementation has introduced additional challenges in voltage drop in PFET and SIR cells. This paper has describes a power gating technique and methodology to address the issues by means optimizing the routing and cell placement density. The effectiveness of this methodology is concluded with close correlation between post-silicon measurement and simulation results.