Lee Kee Yong and Chee Kong Ung
Intel Inc.
As we are marching towards deeper sub-micron technology from process scaling, the transistor leakage itself had became more and more dominant to the total component power, which is unavoidable. Clever employment of power gating / sleep transistor / MTCMOS technology can help to shut off leakage power from un-use blocks. However over placement of power gate cells to reduce ON stage IR voltage drop can yield higher leakage power during OFF stage at high temperature and fast skew. This paper described the circuit analysis, optimization strategies and design methodology to tackle this issue head on. A proposal on power gate placement optimization using the concept of power windowing and Power Perimeter Scan (PPS) was introduced in this paper. Details break down of circuit modeling and design trade off on Power Gating FETs was described including simulation results and equations to aid the illustrations. The overall power saving using MTCMOS was re-evaluated for total leakage minimization. In this paper, a novel power gate placement optimization methodology was presented, to hunt for best optimized power gate cell placement which trade off between OFF stage leakages while not sacrificing the ON stage IR voltage Drop. Using a method called power windowing by perimeter scan coupling with exhaustive search and repair mechanism, a gross 50% improvement on OFF stage leakage was observed using test case while maintaining the IR voltage drop penalties well with-in the design target.