Shu-Han Whi, Bing-Shiun Su, Yu-Min Lee, Chi-Wen Pan
National Chiao Tung University
With the advance of nanometer technologies, the process variations play important roles in integrated circuit designs. The conventional corner value timing analysis becomes less effective and grossly conservative. Given a limited amount of measurement silicon data and without any distribution assumptions, this work develops a spatial correlation estimation methodology with the bootstrap resampling technique to improve the extraction correctness of the spatial correlation. By constructing the confidence interval of the spatial correlation, the correlation between two path delays can be got, and the high coverage rate for the true spatial path delay correlation has been demonstrated from the experimental results.