Philip Beow Yew Tan, Chin Fui Chua, Subhash Chander Rustagi
Silterra Malaysia Sdn. Bhd.
Mechanical stress due to Shallow Trench Isolation (STI) stress has been a subject for investigation for deep sub-micron CMOS processes as it significantly changes the effective carriers’ mobility. We have previously found that when saturation drain current (Idsat) plotted against channel width, decreases when width reduced to W = 1um and then start increasing when width reduced to W=0.15um. This makes Idsat curve looks like a hook. In this paper, we demonstrated that by introducing the high tensile Inter Layer Dielectric (ILD) in the fabrication process, the hook shaped saturation drain current (Idsat) behavior of MOSFET can be reduced in NMOS and totally eliminated in PMOS for 0.13um technology node. The hook shaped Idsat behavior has been discussed in our previous study to be caused by the combination effects of mechanical Shallow Trench Isolation (STI) stress in channel width direction and delta width. This paper explained how the tensile ILD layer on top of the transistor changes the STI stress effect of NMOS and PMOS transistors. The effects on STI stress in channel length direction (x-stress) and channel width direction (y-stress) are discussed. This ultimately changes the hook shaped Idsat behavior of NMOS and PMOS transistors.