Tutorials at ASQED 2012

DFM Fundamentals and new Challenges at Advanced Nodes

Jeff Wilson
DFM Product Marketing Manager
Mentor Graphic, USA

Design For Manufacturing (DFM) is an overused term meaning many different things to different people. This presentation will review the fundamentals of DFM with a brief look at its history, how it has been used to date, and the driving forces behind its adoption. Since the DFM market is still evolving in a number of ways, we will next look at the new challenges at leading edge nodes, and how DFM approaches help overcome the limitations of manufacturing technology. The last part of the presentation will be a look forward to key business issues and technical challenges around the corner for DFM.

About Jeff Wilson

Jeff Wilson is a DFM Product Marketing Manager in Mentor Graphics' Calibre organization. He is responsible for the development of products that address the challenges of CMP and CAA. He previously worked at Motorola and SCS. Jeff received a BS in Design Engineering from Brigham Young University and an MBA from the University of Oregon.

Design, Fabrication and Reliability of Through Silicon Via (TSV) and Silicon Interposer for Robust 3D IC Integration

Farhang Yazdani
Founder and President
Broadpak, USA

Ubiquitous 3D IC integration offers numerous benefits, notably, higher bandwidth, smaller footprint and lower power. 3D/2.5D approaches, such as interposers, enable heterogeneous device integration at virtually any process node. One of the key challenges in 3D integration is controlling the stresses within the device, not only during wafer fabrication, but also during packaging and assembly. Architecting a cost effective and robust interposer that satisfies the signal/power integrity requirement and stress management is key to a successful 3D integration. This presentation covers the fundamentals of Through Silicon Via (TSV) and silicon interposer technology, design architecture, signal integrity, fabrication process and stress management techniques used for robust 3D integration.

About Farhang Yazdani

Farhang Yazdani is the President and Chief Technical Officer of BroadPak Corporation. With over 18 years of experience in semiconductor packaging industry, he is widely regarded as an expert on 3D packaging technologies. Previously, he served in various management, technical and advisory positions with leading semiconductor companies worldwide. He has numerous publications and US patents issued and pending in the area of Packaging and Assembly, serves on various technical committees and is a frequent reviewer for IEEE Journal of Advanced Packaging. He has undergraduate and graduate degrees in Chemical Engineering and Mechanical Engineering from the University of Washington, Seattle. He is a member of AICHE, ASME, IEEE, IMAPS, SPE and the Society of Rheology.

Low Power Techniques for nanometer VLSI Circuits and challenges

Dr. Rajiv Joshi
IEEE Fellow, ISQED Fellow
IBM, USA

Rajiv Joshi &Rouwaida Kanj, IBM

Power has become the key driving force in processor design as the frequency scale-up is reaching saturation.. In order to achieve low power system circuit and technology co-design is essential. This talk focuses on technology and important circuit techniques for nanoscale VLSI circuits.. Achieving low power and high performance is always difficult. Technology has seen major shifts from bulk to SOI and then to non-planar devices such as FinFET and Trigates. The talk consists of pros and cons of technology from power perspective and techniques to exploit lower power. As the technology pushes towards sub-65nm era, process variability and geometric variation in devices can cause variation in power. The reliability also plays an important role in the power-performance envelope. The talk outlines the methodology to capture such effects. All the power components are described All the key areas of low power optimization such as reduction in active power, leakage power, short circuit power and collision power are covered.. Usage of Clock gating, power gating, longer channel, mult-Vt design, stacking, header-footer device techniques and other methods are described for logic and memory. Finally the talk summarizes key challenges in achieving low power.

About Rajiv Joshi

Dr. Rajiv V. Joshi is a research staff member at T. J. Watson research center, IBM. He received his B.Tech degree from Indian Institute of Technology (Bombay, India), M.S degree from Massachusettes Institute of Technology and Doctorate in Eng. Science from Columbia University, USA. He joined IBM in Nov. 1983, and since then is working in VLSI design systems, science and technology. He contributed through innovative process for variety of technology nodes starting from 1.25μm NMOS, and CMOS, logic, and memory technologies. He developed novel interconnect processes and structures for aluminum, tungsten and copper technologies which are widely used in IBM for various sub-0.5μm memory and logic technologies as well as across the globe. His circuit related work includes design of register files, registers, latches, and caches, development of physical design tools, and CAD-based library generation and circuit designs in SOI technology. He received an IBM outstanding technical achievement award for his contributions to IBM microprocessor designs. His recent work related to 8T stable 6 GHz SRAM cell was covered by EE times. He contributed through IP and designs to IBM PowerPC program taking leadership role in SRAM technology, cell analysis/modeling and stability enhancement. He has led successfully pervasive statistical methodology for yield prediction and also the technology-driven SRAM at IBM Server Group. He drove the efforts to commercialize this methodology in 2011 through IP licensing. He has won 53 invention plateau achievement awards from IBM. He received three Corporate Patent Portfolio awards from IBM for licensing contributions. He is a Master Inventor & key technical leader at IBM Research Division. He received "Distinguished Alumnus" award from Indian Institute of Technology in 2008. He has authored and co-authored over 160 research papers and presented several invited and keynote talks. He holds 180 U.S. patents with over 350 total internationally issued patents. He received the Lewis Winner Award in 1992 for an outstanding paper he co-authored at the International Solid State Circuit Conference. He also received prestigious best paper award from ICCAD in 2009. He was instrumental in starting interconnect workshop in early 1980s. He chaired advanced interconnect conferences sponsored by MRS and served as an editor of the proceedings. He is a fellow of IEEE and ISQED and serves as an Associate Editor of TVLSI. He served on committees of ISLPED (Int. Symposium Low Power Electronic Design), IEEE VLSI design, IEEE Int. SOI conf ISQED and Advanced Metallization Program committees.

Manufacturing Testing of VLSI Circuits With Close Focus On Scan-Based Testing

Prof. Ozgur Sinanoglu
Computer Engineering Department
New York University Abu Dhabi (NYUAD)

Ever increasing complexity of designs coupled with newly emerging types of manufacturing defects due to smaller feature sizes poses challenges in high quality and low cost test of manufactured chips. Test is a recurring cost, as it is applied to every single manufactured chip, constituting about 25-30% of the overall production cost today. Low cost test solutions aim at reaching high quality levels (screening out most of the defective parts) while controlling the costs involved. This tutorial covers recent test techniques focusing in particular on scan-based testing. The topics covered are: manufacturing flow and defects; manufacturing test; test quality, defect level and yield; test flow (fault models, ATPG and fault simulation); scan-based testing (static and at-speed test) and costs of test (test time, data volume, and power dissipation); test compression, low power test techniques and adaptive testing.

About Ozgur Sinanoglu

Prof. Ozgur Sinanoglu is with the Faculty of Engineering at New York University in Abu Dhabi. He obtained his Ph.D. in Computer Science and Engineering from University of California, San Diego, in 2004. During his PhD, he was given the IBM PhD Fellowship Award in two consecutive years in 2001 and 2002, and his PhD thesis won the CSE PhD Dissertation Award in UCSD in 2005. He worked for two years at Qualcomm in San Diego as a senior Design-for-Testability engineer, primarily responsible for developing cost-effective test solutions for low-power SOCs. After a 4-year academic experience at Kuwait University, where he was given two research awards, he has joined in Fall 2010 New York University in Abu Dhabi. Upon spending his integration year as a visiting Faculty in New York at the ECE Department of NYU Poly, he joined the Faculty in Abu Dhabi in Fall 2011. His primary field of research is the reliability and security of integrated circuits, mostly focusing on CAD tool development. He has more than 90 conference and journal papers in addition to 3 issued and several pending patents. He is also the recipient of the best paper award of VLSI Test Symposium 2011.

Advanced DFT and BIST Techniques for the Nano-Era

Dr. Adam Osseiran
Managing Director at NNTTF
A/Prof at Edith Cowan University, Australia

The objective of this tutorial is to provide attendees with a summary of advanced DFT (Design for Test) and BIST (Bulit in Self Test) techniques for designs in the nano-era. Overview of traditional fault modeling and recent development in fault models for current and future technologies (e.g., 0.13um, 65nm and below) is given. State-of-the art and novel BIST architectures for digital circuits and memory are covered. The latest challenges and the corresponding BIST techniques for System-on-Chip and the 3D circuits are also presented. Finally, future challenges of mixed-signal testing and BIST are highlighted.

About Adam Osseiran

Associate Professor Adam Osseiran is the Director of the Australian National Networked TeleTest Facility for Integrated Systems (NNTTF) (http://teletest.org.au) and is with the School of Engineering of Edith Cowan University in Western Australia. Dr Adam Osseiran received his B.Sc. (1981) and M.Sc. (1982) from the University Joseph Fourier in Grenoble-France. He received a Ph.D. in microelectronics (1986) from the INPG, National Polytechnic Institute of Grenoble in France. In 1999 he became the European Technical Manager for Opmaxx Inc. a US start-up Company, and participated in its transformation into Fluence Technology. In 2000 he became Technical Director at Integrated Measurement Systems (IMS), Oregon based company specialised in the Design for Test and Built-In Self-Test techniques for Integrated Circuits. From 2000 to 2005 he was the Chair of the International Working Group of the IEEE Std 1149.4 Mixed-Signal Test Bus Standard. He is Vice Chair of the Test Technology Technical Council Asia and is a Senior Member of the IEEE. Since 2004 he has been a reviewer of the Test Technology Educational Program assessing the quality of tutorials to be provided by test educators at the major TTTC conferences.