Tutorials at ASQED 2010
ESD + RFIC Co-Design for Whole-Chip Design Optimization
Albert WangProfessor of Electrical and Computer Engineering
Dept of Electrical Engineering
University of California
ESD (Electro-Static Discharge) failure becomes a major IC reliability problem as semiconductor IC technologies continue migrate into the VDSM (very-deep-sub-micron) regime. On-chip ESD protection design emerges as a grand challenge to RF IC designs recently as stated in the ITRS. While RF ICs typically demand for higher ESD protection, RF circuit is also extremely sensitive to any parasitic effects inherently associated with ESD protection structures, which inevitably affect RF IC circuit performance. This tutorial discusses critical aspects in practical designs, including a mixed-mode ESD simulation-design method for RF ESD protection design prediction, advanced RF ESD protection design and optimization, accurate RF ESD design characterization techniques, complex ESD-circuit interaction effects, ESD-RFIC co-design method for whole-chip design optimization, etc. Practical ESD-aware RF IC design examples will be presented.
About Albert Wang
Prof. Wang's research interests center on RF/Analog/Mixed-Signal Integrated Circuits, Design for Reliability for ICs, SoC, IC CAD and Modeling, Emerging technologies, etc. His academic credits include one book entitled “On-Chip ESD Protection for Integrated Circuits” (Kluwer, 2002), 150+ peer-reviewed papers and several U.S. patents. He received the BSEE degree from Tsinghua University, China, and PhD EE degree from State University of New York at Buffalo, in 1985 and 1996, respectively. From 1995 to 1998, he was with National Semiconductor Corp. in the Silicon Valley. From 1998-2007, he was a professor at the Illinois Institute of Technology, (Electrical & Computing Engineering). Since 2007, he is a professor at the University of California and Director for the Laboratory for Integrated Circuits and Systems.
Planar and Nonplanar Structures Thermal Modelling Studies
Rajiv V. JoshiResearch Scientist
IBM T.J. Watson Research Center NY
As silicon process technology, driven by improved performance requirements, migrates to non-planar devices, thin silicon based devices, 3-D stacking, low resistivity metals and low-k dielectrics, the thermal properties of these materials play a significant role in determining the temperature build-up, power and performance of the chip as well as leakages. The tutorial tries to comprehensively capture modeling of thermal analysis of device front and back end interconnects, temperature measurement and thermal impact on 3D structures. Thermal sensors based on poly-gate as well as diode based devices are described. The impact of bonding structure, multilevel dielectric on temperature is shown. A methodology based on electrothermal coupling is presented to study the impact on power and performance. The application to critical circuits is demonstrated. Finally the course summarizes findings such as self-heating effects, joule heating and electro thermal coupling are some of the key parameters in modeling the accurate behavior of temperature.
About Rajiv V. Joshi
Dr. Rajiv V. Joshi is involved in the development of metallization schemes for VLSI circuits. He obtained his PhD (1990) at the Columbia University, New York, Masters of Engineering (1981) Manufacturing Science and the Massachusettes Institute of Technology Cambridge, Masters of Science (1979) Mechanical Engineering, University of Maine, Maine, Orono and Bachelor Science (1977), Mechanical Engineering, Indian Institute of Technology, Bombay, India. He had specific training in custom integrated design of VLSI in IBM, and works extensively in VLSI design, microelectronics, materials science at MIT and Columbia University. His recent awards include IEEE/ACM William J. McCalla ICCAD Best Paper Award ICCAD 2009, & Outstanding Contribution Award for Statistical Methodology and tool (2008). Dr. Joshi is an IEEE Fellow.
Terascale Computing and Interconnect Challenges: 3D Stacking Considerations
Tanay KarnikProgram Director
Intel
This presentation will introduce technology scaling trends and new challenges. We are at an I/O inflection point due to Tera-scale computing needs. The tutorial will describe the implication to I/O and memory bandwidth and present various options. 3D integration will be presented in detail with die/wafer stacking considerations.
About Tanay Karnik,
Dr. Tanay Karnik (M'88, SM'04) is Program Director in Intel’s Corporate External Research Office. He received his Ph.D. in Computer Engineering from the University of Illinois at Urbana-Champaign in 1995. His research interests are in the areas of variation tolerance, power delivery, soft errors and physical design. He has published over 40 technical papers, has 44 issued and 33 pending patents in these areas. He received an Intel Achievement Award for the pioneering work on integrated power delivery. He has presented several invited talks and tutorials, and has served on 5 PhD students' committees. He was a member of ISSCC, DAC, ICCAD, ICICDT and ISQED program committees and JSSC, TCAD, TVLSI, TCAS review.
IPC Standards and Electronics Manufacturing Environment
David W. BergmanVice President
IPC
Many will look to IPC standards for advice or workmanship requirements for electronic assemblies. Some will find a copy of IPC-A-610 Acceptability of Electronic Assemblies and stop there. But IPC has many other tools that can help improve quality and reliability for companies involved in manufacturing electronics. This presentation will tour the factory floor and point out some of the best and often overlooked resources from IPC.
About David W. Bergman
David W. Bergman is Vice President of International Relations for IPC the Association Connecting Electronics Industries. He has worked at IPC for over 30 years of which more than 25 were as part of the staff team responsible for IPC standardization efforts, education and certification programs. In his current role in International Relations, David is responsible for the globalization effort s of IPC including IPC’s China staff and representatives in Europe and Russia. David is also responsible for joint activities with related sister organizations and was selected to serve 10 years as Secretary General of the World Electronic Circuit Council. In recognition of his efforts to identify alternatives to CFCs for defluxing Printed Wiring Board Assemblies, David was awarded the U.S. EPA's Stratospheric Ozone Protection Award as well as EPA’s "Best of the Best" Stratospheric Ozone Protection Award. He is also a recipient of Soldertec Global’s Lead Free Solder Award. David has degrees in Biology and Chemistry for the University of Illinois-Chicago.