ASQED 2009 Keynote Speakers
A New World of Partnerships for 22nm and Below
Dr. Chi Foon ChanPresident & COO
Synopsys
In less than 10 years our industry has matured considerably.We no longer chase performance through scaling but design sophisticated multi-disciplined systems.Design challenges such as power and signal integrity that were only secondary concerns are now primary. Critical dimensions are measured in multiples of atoms, and the foundry rule lists become longer and longer. Today we are pushing the limits of physics at 22nm and below.
Beyond CMOS we see increasingly complex chips that are merging analog with digital and wireless, including MEMS and other organic-based materials encapsulated in SIPs.How will we accomplish this level of complexity while maintaining high quality, reliability and low cost development in ever-narrowing market windows?The designs of tomorrow require broad-based partnerships and alliances that surpass today’s practices and incorporate all players working closely from product inception to tapeout.
About Chi Foon Chan
Dr. Chi-Foon Chan shares responsibility for running the company with Synopsys chairman and CEO Dr. Aart de Geus. Dr. Chan is focused on driving the company's internal operations and worldwide field organization. He joined Synopsys in 1990 as vice president of Applications and Services. Previously at NEC Corporation, Dr. Chan was general manager of the microprocessor group, responsible for marketing all NEC chip devices in North America. Prior to NEC, Dr. Chan was an engineering manager at Intel Corporation. He holds an M.S. and a Ph.D. in Computer Engineering from Case Western Reserve University.
The Present Status and Issues in Solar Photovoltaic Systems
Professor Takashi TomitaSolar Quest, RCAST
University of Tokyo
According to World Energy Outlook 2007, IPCC and IEA refer to the crisis of global warming due to the abuse of fossil fuel. One significant measure to mitigate this issue is to increase clean electricity source based on renewable energy. This paper describes the present status and discusses on technical issues of Solar Photovoltaic Systems (PV). PV has been expected to be one of promising candidates for next power generation. It isbecause of abundant solar irradiation and no CO2 emission during the operation. In recent years, remarkable progress has been made in the exploitation of PV in Europe, Japan and US. The world capacity of installation exceeds to more than 10GW until 2009. Admirable success seems to stem from the simplicity of crystalline silicon technology (called 1stgeneration) and the effectiveness of strategic incentives into the market. The issue of PV still remains in relatively high cost in electricity generation and its installation, comparing with conventional power generation (coal, LNG, nuclear). Intensive efforts need to be made in the promotion of both various cell architectures (2nd generation) and interconnection methods with grids. The key to cost-down is in the improvement in conversion efficiency of PV. This paper focuses on the topics of advanced science and technology on semiconductor devices and upcoming PV applications including decentralized power generation with PLC.The recent discussion on Smart Grid which is associated with advanced grid connection of PVs, will be also added.
About Takashi Tomita
Takashi Tomita now serves as Visiting Professor of the University of Tokyo, Research Center of Advanced Science and Technology; and as a Member of the Market Strategy Board of the International Electro-technical Commission (IEC).Prior to this, Tomita provided 34 years of successful leadership at SHARP Corporation.As an Executive Director of Sharp and head of the Solar Business Group, Tomita guided the company to become the largest solar supplier in the world for seven consecutive years, achieved a total solar business volume of $1.5bn in 2006, and established Sharp as the top residential solar supplier in Japan.Tomita has contributed new technologies into the field of crystalline silicon cell/modules, amorphous/ micro-crystalline silicon thin film processes, and 3-5 compound semiconductor cells/ concentrators.Professor Tomita is a specialist in Semiconductor Physics, Solid State Electronics, Optical Processes, and Microwave Electronics.He actively supports the Solar Industry, having served as Committee Member of Renewable Energy Portfolio Standard of METI, Advisory Board Member of the NARA Advanced and Technology Institute, and Visiting Professor of Tohoku University.
IC Packaging Technology - Electronic's New Gatekeeper for Cost and Performance
Joseph FjelstadFounder and President
Verdant Electronics
For more than half a century, the electronics industry has relentlessly pursued technological improvements in design and manufacturing to deliver on its long standing tradition of continually improving performance and reliability while reducing cost. Over that time, most of the gains have been realized by continuous improvement in the manufacturing processes of semiconductor devices. As Moore's Law now is confronting the reality of physics, and the age of doubling of transistors every 24 months draws to a close, IC packaging technology is rapidly rising in importance and new methods for interconnecting and packaging IC are being developed to continue the march of progress but now into the third dimension where stacking of chips and packages promise to continue to meet long standing expectations. This presentation will look both backward and forward in time to briefly explore the past. present and future of IC packaging and examine some of the challenges that lay ahead.
About Joseph Fjelstad
Verdant Electronics founder and President Joseph (Joe) Fjelstad has more than 35 years of international experience in electronic interconnection and packaging technology in a variety of capacities from chemist to process engineer and from international consultant to CEO. Mr. Fjelstad is also a well known author and magazine columnist writing on the subject of electronic interconnection technologies. Prior to founding Verdant, Mr. Fjelstad co-founded SiliconPipe a leader in the development of high speed interconnection technologies. He was also formerly with Tessera Technologies, a global leader in chip-scale packaging, where he was appointed to the first corporate fellowship for his innovations.
Trust But Verify – Product Quality in the SoC Era
Dr. Charlie HuangSVP & Chief Strategy Officer
Cadence Design Systems
For decades, chip companies have enjoyed consistent progress as manufacturing and testing technologies scaled to ever-smaller geometries.Product quality was ensured by process control and chip testing.But as the electronics worldcontinues its transition from individual ICs to systems-on-chip (SoCs), design verification is becoming a crucial factor in overall product quality.In systems made from individual ICs, each chip’s design can be verified to perform its own functions correctly before integration with other parts.In SoC designs, boundaries are blurred, no circuit is isolated, and any function or operation may be perturbed by any other operation.
The growing complexity of external features like phone, camera, video, game, and GPS is amplified by internal complications like energy-efficient design, multi-protocol channel management (, )and application integration.The interactions of all these factors produce an exponential increase in the risk of design failure, which can produce schedule delays, increased costs, and defective products.A new and comprehensive verification methodology must be applied to the SoC design process in order to ensure true product quality.
About Charlie Huang
Charlie Huang serves as Cadence Senior Vice President and Chief Strategy Officer. Huang is responsible for finding and evaluating growth opportunities for Cadence in EDA, the adjacencies and in developing markets. Huang also manages the Cadence investment portfolio, which consists of venture capital and direct investments. Dr. Huang co-founded CadMOS Design Technology, a company that provided solutions for signal integrity problems in ultra deep sub-micron processes. As CEO of CadMOS, he raised venture capital from a variety of investors and managed the company through its successful acquisition by Cadence in 2001. Before CadMOS, he was vice president of R&D at EPIC Design Technology, a startup that pioneered static timing analysis, fastmos, and RC extraction technologies for IC designs. After EPIC Design's successful IPO in 1996, it was acquired by Synopsys, where Huang became Vice President of R&D in the EPIC Technology Group. Dr. Huang holds Bachelor of Science degrees in electrical engineering and computer science from Shanghai Jiao Tong University, and an MSEE and Ph.D. in electrical engineering from Carnegie Mellon University. He holds a U.S. patent on piecewise linear event driven simulation.
Variability-Resilient Mixed-Signal IC Design Methods
Dr. Hans RijnsVice President, head of Research
NXP Semiconductors, Netherlands
This keynote will address the various variability causes and effects in advanced CMOS processes and the implication and solutions for Mixed-Signal designs. Circuit operation largely depends on the ability to accurately control and reproduce transistor and process parameters, such as oxide thickness, dielectric constants, doping levels, width and length. Global wafer- and die-level variations in processing have been countered by the definition of process corners and with improved lithography and diffusion process monitoring methodologies presently controlled effectively during fabrication time.
In advanced CMOS processes, local stochastic device-to-device variations have now become the dominant factor that determines the accuracy, yield and reliability of CMOS circuits. Differential mode analog circuits are robust against global variability, but are affected by these random (mismatch) parameter spreads. Digital circuits are typically over-designed with ample headroom to accommodate for this random spread that mainly affects the gate delays.
Next to these static random phenomena, time-dependent variations (supply voltage, temperature, interference and cross-talk) increasingly affect the reliability of the circuit operation of devices that formally meet all functional and parametric production tests.
Understanding and mitigating these different variability effects require new resilient design techniques to compensate for its effects during design- and run-time and therefore an opportunity for competitive differentiation.
About Hans Rijns
Dr. Hans Rijns is Vice President and head of Research at NXP, the independent semiconductor company founded by Philips. Hans is responsible for all applications, systems, circuits and process technology research programs at NXP. In this role, he is part of the NXP Corporate Innovation and Technology management team headed by Rene Penning de Vries. He started his professional career in 1991 at Philips Research as scientist in the area of discrete-time mixed-signal circuits. In 1996 he moved to Philips Semiconductors and held various technical and business management positions mainly in the field of baseband and multimedia products for the wireless market. Since 2006, he proceeded to executive management positions in NXP Research. Hans holds an M.Sc. and Ph.D. in Electrical Engineering from the University of Twente, the Netherlands.