ASQED 2012: Program (rev. 6)
SESSION 1A
Tuesday, July 10, 2012
1:30PM-3:00PM
Design and Optimization of Interconnect
Chair: Abbes Amira, Qatar University
1:30PM
1A.1
A New Design Methodology of Networks on Chip
Ali Mahdoum
Centre de Développement des Technologies Avancées
1:50PM
1A.2
Optimization of Routing Architecture and Performance for FPGA Routing Fabric
Biley Tan
Altera Corporation
2:10PM
1A.3
Parasitic Capacitance and Density Optimization Modeling Fill Synthesis for VLSI Interconnect
Joel Yee Kiat Yeo1, Khine Nyunt2, Hin Yong Wong2
1Intel Microelectronics, 2Multimedia University
2:30PM
1A.4
Accurate and Fast Cell Spreading Technology for Force Directed Placement
Sifei Wang1, Qiang Zhou2, Xu Qian1, Yici Cai2, Wenchao Gao1, Wenjun Zhou1
1School of Mechanical Electronic & Information Engineering, China University of Mining and Technology, 2Dept. of Computer Science & Technology, Tsinghua University
SESSION 1B
Tuesday, July 10, 2012
1:30PM-3:00PM
Memory Circuits
Chair: Kim Tae Hyoung, Nanyang Technological University, Singapore
1:30PM
1B.1
Retention Time Characterization and Optimization of Logic-compatible Embedded DRAM Cells
Anh Tuan Do, He Yi, Kiat Seng Yeo, Tony Tae Hyoung Kim
Nanyang Technological University, Singapore
1:50PM
1B.2
Maximization of SRAM Energy Efficiency Utilizing MTCMOS Technology
Bo Wang1, Jun Zhou2, Tony T. Kim1
1Nanyang Technological University, 2A*STAR Institute of Microelectronics
2:10PM
1B.3
Low-Power and Robust SRAM Cells Based on Asymmetric FinFET Structures
Behzad Ebrahimi, Reza Asadpour, Ali Afzali-Kusha
University of Tehran
2:30PM
1B.4
Process Variation Tolerant SRAM Cell Design Using Additive Model Considering NBTI Effect
Alireza Khosropour, Seyed-Ali Kashani-Gharavi, Reza Asadpour, Ali Afzali-Kusha
University of Tehran
SESSION 2A
Tuesday, July 10, 2012
3:30PM-5:00PM
Device Modeling and Automation for Physical Design
Chair: Young Hwan Kim, POSTECH, Korea
3:30PM
2A.1
Clock Tree Construction Using Gated Clock Cloning
Wun-Han Chen1, Hsin-Hung Chang1, Jui-Hung Hung2, Tsai-Ming Hsieh1
1Department of Information and Computer Engineering, Chung Yuan Christian University, 2Department of Electronic Engineering, Chung Yuan Christian University
3:50PM
2A.2
A Bias-Driven Approach to Improve the Efficiency of Automatic Design Optimization for CMOS OP-Amps
Ya-Fang Cheng, Li-Yu Chan, Yen-Lung Chen, Yu-Ching Liao, Chien-Nan Jimmy Liu
National Central University
4:10PM
2A.3
A Robust Incremental Power Grid Analyzer by Macromodeling Approach and Orthogonal Matching Pursuit
Yi-Hsuan Lee1, Yu-Min Lee1, Liang-Chia Cheng2, Yen-Tang Chang3
1Department of Electrical and Computer Engineering, National Chiao Tung University, 2Information and Communications Research Laboratories, Industrial Technology Research Institute, 3Bureau of Standards, Metrology and Inspection, M.O.E.A., Taiwan
4:30PM
2A.4
Analyzing BTI Effects on Retention Registers
Yao-Te Wang and Ing-Chao Lin
National Cheng Kung University
SESSION 2B
Tuesday, July 10, 2012
3:30PM-5:00PM
Analog Circuits
Chair: Kim Tae Hyoung, Nanyang Technological University, Singapore
3:30PM
2B.1
Low Power AMOLED Driving Scheme based on Reduced Data Supply Voltage
Eun-Ji Song, Hoon Jeong, Hyoungsik Nam
Kyung Hee University
3:50PM
2B.2
0.5 V, 36μW Gm-C Butterworth Low Pass Filter in 0.18μm CMOS process
Vasantha M. Harishchandra and Tonse Laxminidhi
NITK, Surathkal
4:10PM
2B.3
Wideband LNA Design for SDR Radio using Balanced Amplifier Topology
Anwar Faizd Osman and Norlaili Mohd. Noh
USM
4:30PM
2B.4
An All-Digital Clock and Data Recovery Circuit for Spread Spectrum Clocking Applications in 65nm CMOS Technology
Ching-Che Chung1, Duo Sheng2, Yang-Di Lin1
1National Chung Cheng University, 2Fu Jen Catholic University
SESSION 2C
Tuesday, July 10, 2012
3:30PM-5:00PM
Sensors & Nanoelectronics
Chair: Ramgopal Rao, IIT Bombay
3:30PM
2C.1
A Low-Cost Capacitive Relative Humidity Sensor for Food Moisture Monitoring Application
Bo WANG1, Man Kay LAW2, AMINE Bermak1
1HKUST, 2Macao University
3:50PM
2C.2
Junction Temperature Measurements in Packaged p-Ge Infrared Emitter Using Three Different Methods
Wei Ching LIEW1, Chin Peng CHING1, Mutharasu Devarajan2
1University of Science Malaysia, 2
4:10PM
2C.3
Field-Based Parasitic Capacitance Models for 2D and 3D sub-45-nm Interconnect
Aixi Zhang1, Wei Zhao2, Xiaoan Zhu2, Wanling Deng2, Jin He2, Aixin Chen3, Mansun Chan2
1Peking University Shenzhen SOC Key Laboratory, PKU HKUST Shenzhen-Hong Kong Institution, Shenzhen, China; School of Electronic Information Engineering Beijing University of Aeronautics and Astronautics, Beijing, China, 2Peking University Shenzhen SOC Key Laboratory, PKU HKUST Shenzhen-Hong Kong Institution, Shenzhen, China, 3School of Electronic Information Engineering Beijing University of Aeronautics and Astronautics, Beijing, China
SESSION 1P
Tuesday, July 10, 2012
Wednesday, July 11, 2012
11:15AM-12:00
Poster Papers
Chair: Ali A. Iranmanesh, California Polytechnic Institute
1P.1
The Effect of Higher Order Model Decoupling Capacitors in the Design of a Power Delivery Network
LI WERN CHEW
Intel Microelectronics (M) Sdn. Bhd.
1P.2
A Monotonic and Low-Power Digitally Controlled Oscillator Using Standard Cells for SoC Applications
Duo Sheng1, Ching-Che Chung2, Jhih-Ci Lan1
1Fu Jen Catholic University, 2National Chung Cheng University
1P.3
System Management with Relational Database for Mask Tape-Out
Chow Leng Ng, Chiew Har Alfonso Jee, Wai Tat Ow Yong
Spansion
1P.4
Decoupling Capacitor Placer Algorithm with Routing and Area Consideration in VLSI Layout Design
Thomas Fong Chee Goh, Jonathan Yoong Seang Ong, Chun-Keong Lee
Spansion
1P.5
High Inference Speed Analog Fuzzy Logic Controller
VINOD KAPSE1, Dr. BHAVANA JHARIA2, Dr. S.S. THAKUR3
1Research Scholar, Jabalpur Engineering College, Jabalpur, India, 2PROFESSOR,Dept.of Electronics & Communication Engg.,Jabalpur Engineering College, Jabalpur, India, 3PROFESSOR,Dept. of Mathematics,Jabalpur Engineering College, Jabalpur, India
1P.6
Impact on Signal Integrity of Differential Pair Routing Over Split Plane and Voids
Omar Mukhtar Adanan1, Ahmad Jalaluddin Yusof2, Jackson Kong2, Aftanasar Md. Shahar1
1Universiti Sains Malaysia, 2Intel Microelectronic Sdn. Bhd.
1P.7
Robustness Validation of Integrated Circuits and Systems
Martin Barke1, Michael Kärgel2, Weiyun Lu3, Felix Salfelder4, Lars Hedrich4, Markus Olbrich2, Martin Radetzki3, Ulf Schlichtmann1
1Technische Universität München, 2Leibniz Universität Hannover, 3University Stuttgart, 4J. W. Goethe University Frankfurt a.M.
1P.8
3D IC Implementation for MPSOC Architectures: Mesh and Butterfly Based NoC
Omar Hammami1, Abir M'zah1, M.Hairol jabbar2, Dominique Houzet3
1ENSTA Paristech, 2GIPSA lab,ENSTA Paristech,, 3GIPSA lab
1P.9
An Approach to Yield Estimation of Gigascale SoCs
Jairam S
Texas Instrument India
1P.10
Formation of Sn-Bi Alloys through Sequential Electrodeposition
Seen Fang Lee, A.S.M.A. Haseeb, Yingxin Goh
University of Malaya
1P.11
A GA-Based Optimization for Fourth-Order Sallen-Key Low-Pass Filter
Teoh Yeong Yeap and Neoh Siew Chin
School of Microelectronic Engineering, Universiti Malaysia Perlis (UniMAP)
1P.12
Power Awareness for Multi-voltage Island X-Clock Tree Construction with Double-via Insertion
Chia-Chun Tsai1 and Trong-Yen Lee2
1Nanhua University, 2National Taipei University of Tech.
1P.13
Genetic Algorithm-Based Optimization in 4th Order Sallen Key High Pass Filter
Cheng Khye Lun and Neoh Siew Chin
Universiti Malaysia Perlis (UniMAP)
1P.14
Solar Harvested Energy Prediction Algorithm for wireless sensors
Muhammad Hassan and Amine Bermak
HKUST
1P.15
Fabrication and characterization of silicon-based Ba0.7Sr0.3TiO3 thin films for FeFET applications
Ala’eddin Saif and Prabakaran Poopalan
University Malaysia Perlis
SESSION 3A
Wednesday, July 11, 2012
1:30PM-3:00PM
Verification
Chair: Chin Hai Ang, Altera
1:30PM
3A.1
Monte Carlo Simulation In VDDmin Modeling Across Fab Process
Hugo Guo, Yang Yang, Bowen Jiang
LSI Corporation
1:50PM
3A.2
Enhanced Tracing and Visibility in Logic Emulation Environment by Optimized Design Slicing
Somnath Banerjee and Tushar Gupta
Mentor Graphics Pvt. Ltd., India
2:10PM
3A.3
Simultaneous Switching Noise Impact to Signal Eye Diagram on High-Speed I/O
Siang Rui Chan1, Fern Nee Tan2, Rosmiwati Mohd-Mokhtar3
1Intel Microelectronics (M) Sdn. Bhd, Universiti Sains Malaysia, 2Intel Microelectronics (M) Sdn. Bhd, 3Universiti Sains Malaysia
2:30PM
3A.4
Phosphor Concentration Effects on the Thermal and Optical Performance of Cool and Warm White Single Chip Light Emitting Diodes
Hsien Shiung Hwang, Anithambigai Permal, Mutharasu Devarajan
Nano Optoelectronics Research Laboratory, School of Physics, Universiti Sains Malaysia
SESSION 3B
Wednesday, July 11, 2012
1:30PM-3:00PM
Advanced Topics in Circuit and System Design
Chair: Amine Bermak, UST, Hong Kong
1:30PM
3B.1
On Regularity and Integrated DFM Metrics
Kasyab P. Subramaniyan and Per Larsson-Edefors
Chalmers University of Technology
1:50PM
3B.2
Memory Efficient Reliability Assessment for System-Level Design of Embedded Systems
Adeel Israr and Sorin Huss
TU-Darmstadt
2:10PM
3B.3
Load Model Technique for Mesh-structured Power Distribution Network
Hyoeon Yang1, Taeil Bae2, Jinwook Kim1, YoungHwan Kim1
1POSTECH, 2Magnachip
2:30PM
3B.4
A Novel Hardware Implementation for the IEEE 802.22 Turbo-Like Interleaver
Mehdi Ahmadi, Ali Azarpeyvand, Sied Mehdi Fakhraie, Reza Asadpour
University of Tehran
SESSION 3C
Wednesday, July 11, 2012
1:30PM-3:00PM
Advanced Packaging: Signal Integrity & Co-Design
Chair: Farhang Yazdani, BroadPak, USA
1:30PM
3C.1
Analysis of System Bus on SoC Platform Using TSV Interconnection (INVITED)
Kyoungrok Cho, Hyeon-Seok Na, Tae Won Cho, Younggap You
College of Electrical and Computer Eng., Chungbuk Nat'l University
1:50PM
3C.2
Thermal and Optical Analysis of Multi-chip LED Packages with Different Electrical Connection and Driving Current
Ming Yeng Lim, Sik Hong Gan, Sze Yen Lee, Zhi Yin Lee, Mutharasu Devarajan
Universiti Sains Malaysia
2:10PM
3C.3
Structural Package and Board Design Approach for System-on-Chip Power Delivery Analysis
Wai Ling Lee and Li Chuang Quek
Intel Microelectronic (M) Sdn. Bhd
2:30PM
3C.4
Signaling Analysis of Inter-Chip I/O Package Routing for Multi-Chip Package
Khang Choong Yong1, Wil Choon Song1, Bok Eng Cheah1, Mohd Fadzil Ain2
1Intel Microelectronics (M) Sdn. Bhd, Halaman Kg. Jawa, Penang, Malaysia, 2School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Penang, Malaysia
SESSION 4A
Wednesday, July 11, 2012
3:30PM-5:00PM
Test
Chair: Chin Hai Ang, Altera
3:30PM
4A.1
DFT-STA Collaboration to improve test quality: A case study
Naishad Parikh and Gautam Kale
Texas Instruments
3:50PM
4A.2
A Methodology For LBIST Logic Diagnosis In High Volume Manufacturing
Andal Jayalakshmi and Tan Ewe Cheong
Intel
4:10PM
4A.3
Fully Synthesizable Delay Cell Design for Emulation Environment
Kok Khim Tee and Thiam Ern Lim
Intel Microelectronics (M)
4:30PM
4A.4
Delay-Line Based Embedded Memory Access Time Measurement: Circuit, Implementation and Characterization Techniques
Moo Kit Lee, Wei Khoon Teng, Raj Kumar Krishnasamy, Wei Tee Ng
Marvell Semiconductor Sdn. Bhd.
4:50PM
4A.5
Unified Model for Analyzing Timing Delay and Crosstalk Effects in Carbon Nanotube Interconnects
Debaprasad Das and Hafizur Rahaman
Bengal Engineering and Science University, Shibpur, India
SESSION 4B
Wednesday, July 11, 2012
3:30PM-5:00PM
Digital VLSI and High Speed Interfaces
Chair: Sze Wei Ong, Intel
3:30PM
4B.1
Design of a Wave-Pipelined Serializer-Deserializer with an Asynchronous Protocol for High Speed Interfaces
Chinh Hien Bui, Seok-Man Kim, Kyoungrok Cho
Chungbuk National University, Korea
3:50PM
4B.2
Soft-Error Hardened Redundant Triggered Latch
Hossein Karimiyan Alidash1, Sayed Masoud Sayedi2, Vojin G. Oklobdzija3
1University of Kashan, 2Isfahan University of Technology, 3New Mexico State University
4:10PM
4B.3
A 2.5-12.5Gbps Interpolator-based Clock and Data Recovery Circuit for FPGA
Lip-Kai Soh and Wai-Tat Wong
Altera Corporation
4:30PM
4B.4
NoC-based MPSoC Design and Implementation on FPGA: DCT Application
Omar HAMMAMI and Mohamed JABBAR
ENSTA PARISTECH
SESSION 4C
Wednesday, July 11, 2012
3:30PM-5:00PM
Advanced Packaging: Process Technology
Chair: Farhang Yazdani, BroadPak, USA
3:30PM
4C.1
Effects of Sn Concentration and Current Density on SnBi Electrodeposition in Additive Free Plating Bath
Ying Heong Chiew, A.S.M.A. Haseeb, Yingxin Goh, Seen Fang Lee
University of Malaya
3:50PM
4C.2
Effects of Thiourea and Gelatin on the Electrodeposition of Sn-Ag Solder Alloy
Xin Wei Lee, A.S.M.A. Haseeb, Yingxin Goh
University of Malaya
4:10PM
4C.3
Effects of Mn nanoparticles on wettability and intermetallic compounds in between Sn-3.8Ag-0.7Cu and Cu substrate during multiple reflow
Kai Xiang Koh, A.S.M.A Haseeb, M.M Arafat, Yingxin Goh
University of Malaya
4:30PM
4C.4
Packaging Performance of GaAs/InGaAs/InGaP Collector-Up HBTs as Power Amplifiers
Hsien-Cheng Tseng and Wen-Jinn Chu
Kun Shan University
4:50PM
4C.5
Effects of Hydroquinone and Gelatin on the Electrodeposition of SnBi Low Temperature Pb-Free Solder
Yingxin Goh, A.S.M.A. Haseeb, Mohd Faizul Mohd Sabri
University of Malaya, Kuala Lumpur, Malaysia