Abstract: As technology continues to scale beyond 65nm and increase in design complexity of a System-On-Chip (SoC) accommodating 100s of Ks of flops, multi OPP (Operating Performance Points) scaling, 100s of clock domains, low power and compact die requirements poses a set of challenges to meet Design for testability (DFT) coverage goals without impacting other design goals. To overcome these challenges, DFT and Static Timing Analysis (STA) teams collaborated on various strategies ranging from modifications in test clock architecture to test clocks grouping and SDC (Synopsys Design Constraints) based flow to recover coverage lost during final design closure cycles. We present these strategies in form of a case-study, to find a balance point where both DFT and design goals are met without trading one for another.