Field-Based Parasitic Capacitance Models for 2D and 3D sub-45-nm Interconnect

Aixi Zhang1,  Wei Zhao2,  Xiaoan Zhu2,  Wanling Deng2,  Jin He2,  Aixin Chen3,  Mansun Chan2
1Peking University Shenzhen SOC Key Laboratory, PKU HKUST Shenzhen-Hong Kong Institution, Shenzhen, China; School of Electronic Information Engineering Beijing University of Aeronautics and Astronautics, Beijing, China, 2Peking University Shenzhen SOC Key Laboratory, PKU HKUST Shenzhen-Hong Kong Institution, Shenzhen, China, 3School of Electronic Information Engineering Beijing University of Aeronautics and Astronautics, Beijing, China

Abstract

In the design of scaling complementary metal-oxide-semiconductor (CMOS), back-end-of-the-line (BEOL) interconnection becomes a limiting factor to circuit performance. Compact models for paratactic capacitance, which are scalable with wire geometries, are desired for circuit simulation and design. Considering both two-dimensional and three-dimensional single wire above plate, the proposed method decomposes the electric field into various regions and gives solutions for each part. The total ground capacitance is the summation of all components. The solution can be easily extended to the case of two parallel wires. Its physical base minimizes the complexity and error comparing with a traditional model fitting process. The new compact model has been verified with COMSOL simulations. It accurately predicts the capacitance for not only the nominal wire dimensions from the latest ITRS updates, but also for a wide range of other BEOL wire dimensions.