In this paper, we present different designs for hardware implementation of the IEEE 802.22 Turbo-Like Interleaver. In addition to classical approaches such as direct and ROM-based implementation, a novel architecture is proposed. All of the new and classical designs are implemented using VHDL, synthesized with the 180 nm typical TSMC technology files and compared in terms of area, power and delay. Based on the simulation results, the proposed method results in 33% and 46% improvement in terms of area and power compared to the direct method. It also shows 88% saving in area and 46% reduction in power consumption rather than ROM-based method. Furthermore, its operating frequency meets the standard requirements