Online Error Detection in SRAM based FPGAs using Scalable Error Detection Coding

Zahid Ali Siddiqui and Jeong-A Lee
Chosun University


SRAM based devices are more susceptible to unidirectional errors when exposed to radiations. This paper presents an error detection scheme for detecting errors in SRAM cells of FPGA. This proposed Scalable Error Detection Coding (SEDC) scheme is capable of detecting 100% unidirectional errors. SEDC scheme partitions the data into segments of 2-, 3- and 4-bits data and encodes those segments using SEDC codes, in parallel fashion. The programming device generates the SEDC check bits along with the configuration bits and stores them on the FPGA’s SRAM cells. All unidirectional errors in SRAM cells, caused by cosmic radiations, are detected by a high speed, compact and easily scalable totally self-checking SEDC checker, whose implementation details are presented in this paper. The proposed technique achieves significant improvement in area as well as speed over Berger technique [12] for the same application.

[12] [12] D. A. Pierce. Jr and P. K. Lala, “Modular implementation of efficient self-checking checkers for the Berger code,” J. Electron. Test., vol. 9, pp-279-294, December 1996.