In real-time data-dominated communication and multimedia processing applications, data transfer and storage significantly influence, if not dominate, all the major cost parameters of the design space – namely power consumption, performance, and chip area. Multilayer memory hierarchies are used to reduce the energy consumption, but also to enhance the system performance. The energy-aware optimization of a hierarchical memory architecture implies the addition of layers of smaller and faster memories used to store the intensely-used data, in order to better exploit the non-uniform memory accesses. This paper presents an electronic design automation (EDA) methodology for energy-efficient signal assignment to the memory layers of a hierarchical storage organization. This approach starts from the behavioral specification of a given application and, employing algebraic techniques specific to the data-dependence analysis used in modern compilers, identifies those parts of (multidimensional) arrays intensely accessed. Tested on a two-layer memory hierarchy, this EDA methodology led to savings of storage energy consumption from 40% to over 60% relative to the energy used in the case of flat memory designs.