The paper proposes an FPGA-like approach to on-chip communication and comes up with a design methodology where switches are avoided and where two any IPs are connected if and only if they are communicating. It avoids the problem of costly (time, area, energy) intermediate hop counts of on-chip networks (NOCs) between any two source-destination pairs. The second novelty is that without knowing the overlap/disjointness of communication packets between any two IP blocks, a designer may use unnecessary resources (wasting time, space, energy, resources, etc). So, we look into the temporal aspect of communication and then it is possible that some communication phases don’t overlap, thus a designer needs not provision resources for such cases. Based on this methodology, our CAD tool aims at designing NOCs subject to bandwidth, area and energy constraints.