The era of multiprocessor system-on-chip (MPSoC) has brought a new challenge for modern electronic systems. Communication between IP cores and other peripheral in the MPSoC environment is becoming critical which will affect the performance. Network-on-Chip (NoC) is a promising solution for MPSoC communication limitation. Several NoC studies have been reported over the years but only a few discussed about the actual hardware implementation. In this paper, we presented FPGA design and implementation of MPSoC system with NoC architectures in order to obtain its actual performance. A case study of Discrete Cosine Transform (DCT) using parallel programming is carried out to validate the design.