With technology scaling beyond 90 nm, the impact of process variation on failure of static random access memories (SRAM) is becoming more significant than any time before. In this paper we will discuss statistical design methodology for a 6T SRAM cell in 45nm technology taking into account for these variations. In this work the design parameters are widths and lengths of 6 transistors in the cell. We will use a new statistical modeling scheme based on nonlinear regression in order to model statistical distribution of different SRAM reliability metrics such as SNM, Read Current and Vtrip with more accuracy. Also we will introduce a new method to estimate SRAM block leakage distribution. We will utilize our proposed models in order to design a process variation tolerant, low power SRAM cell taking into account for maximum area constraint.