Load Model Technique for Mesh-structured Power Distribution Network

Hyoeon Yang1,  Taeil Bae2,  Jinwook Kim1,  YoungHwan Kim1
1POSTECH, 2Magnachip


This paper proposes an efficient load model for power network noise analysis. The proposed method approximates an uninteresting part of a large mesh-structured circuit to a simple load model which consists of a couple of RLC elements. In the experimental results, the proposed method reduced a CPU time of SPICE simulation by up to 95% while suppressing the maximum and average voltage errors less than 0.0207 and 0.0048 respectively.