Process variation in scaled technologies pose a major challenge for design of high peformance ASICs. The yield of CMOS logic circuits satisfying a specic high performance requirement is signicantly influenced by the magnitude of critical path delay deviations. This paper dis- cusses the effect of process variation in reducing the yield with respect to the maximum clock frequency of operation. A method to estimate the yield has been proposed by con- structing the probability distribution of the critical path delay and the maximum clock frequency (fmax). This dis- tribution is constructed from simulation of various device and circuit models. The obtained distribution has been compared with statistical simulation results.