Memory Efficient Reliability Assessment for System-Level Design of Embedded Systems

Adeel Israr and Sorin Huss


Permanent and soft errors are inherently different in property and effect on the functionality of systems. This paper shows how to utilize this fact to develop reliable embedded systems. Based on an introduction of System Decision Diagrams a couple of new data structures denoted as System Resource Decision Diagram and System Task Instance Decision Diagram, respectively, are proposed, which are based on the zero-suppressed binary decision diagram. The first data structure deals with the permanent errors occurring in the system, whereas the second one represents the effects soft errors have on the system's functionality. Both the construction of this diagram pair and the memory-aware evaluation of the reliability based on it are detailed in an algorithmic way. The error model representation and the reliability quantification approach are aimed to be employed in a system-level design process in order to accelerate design space exploration.

The proposed method is illustrated for a number of benchmarks taken from published papers. The achieved results demonstrate that this novel approach is highly memory efficient and at the same time accurate as compared to previous known schemes.