Enhanced Tracing and Visibility in Logic Emulation Environment by Optimized Design Slicing

Somnath Banerjee and Tushar Gupta
Mentor Graphics Pvt. Ltd., India


Field Programmable Gate Array (FPGA) based logic emulators, used for functional verification of large and complex System-on-chip (SoC) designs are characterized by two conflicting requirements – execution speed and signal visibility. Achieving 100% signal visibility in post-processing debug for long emulation runs impacts execution speed and requires large amount of disk space. Techniques like combinational reconstruction, periodic snapshot based tracing, state restoration etc. have reduced the amount of trace data and hence the impact on execution speed to some extent, but fail to provide a scalable solution for growing design sizes. Selective tracing based on signal list specification does not guarantee tracing all relevant signals needed to be investigated to debug a functional mismatch, often requiring re-runs to generate relevant data. This paper presents a novel tracing and visibility system based on the concept of optimized design slicing (ODS), which minimizes trace data while providing sufficient debug visibility by tracing only a set of design portions or “slices” that are likely to affect values of a set of “observed variables”, or in other words influence a set of properties under verification. These slices are extracted automatically from the design logic and capture all the signals likely to impact the observed variables, ensuring sufficient debug visibility. The slices are “optimized” by techniques like software memory replay and blackbox elimination. The proposed system achieves effective reduction in trace data, higher execution speed and provides necessary debug visibility for post-processing debug.