Structural Package and Board Design Approach for System-on-Chip Power Delivery Analysis

Wai Ling Lee and Li Chuang Quek
Intel Microelectronic (M) Sdn. Bhd


As fabrication technology process shrinking and the increasing circuit design complexity, design target become more stringent. Power delivery design getting more challenging to ensure no device functional failure in the low power design trend. With manufacturing cost coming into picture, platform power delivery is playing an essential part in providing robust electrical solution by determining the need of package and board capacitor placement. Further more, there is hidden challenge as power delivery engineer do not design details to start power delivery design, for instance package stack-up and number of layer, platform size and so on. As marching toward system-on-chip design world, it is time to change current power delivery working model from passive to active role. This paper explains how power delivery team performs electrical estimation by characterizing via parasitic, power and ground separation as well as package and board dimension. This approach can be applied at both early product definition phase and end phase of design cycle; for early platform design space requirement assessment and quick sanity check on electrical performance after platform routing completed. Later section of this paper shows correlation results of estimation model and FEM tool simulated model fall in 20% range for selected test case.