A Methodology For LBIST Logic Diagnosis In High Volume Manufacturing

Andal Jayalakshmi and Tan Ewe Cheong


LBIST (Logic Built-In Self Test) are structural test methods that test a circuit by running test patterns generated on the die as opposed to ATPG (Automatic Test Pattern Generation) method which generates patterns for every possible fault that can happen in the circuit. LBIST has emerged as an alternative scan based test methodology due to its attractive benefits such as reduced pattern size and field testability. LBIST uses pseudo random patterns enabling it to generate patterns on the die saving tester memory to a large extent. At the same time it poses challenges to enable fail data collection for later debug as the LBIST test iterations are usually large (typically 100000). Tester time is not a big concern for a LBIST based method if the objective is to know if the unit passed or failed, but memory usage is a concern due to the need to compare intermediate scan responses to determine and collect failing responses for diagnosis and debug purposes. This motivated us to come up with a methodology for fail data collection that takes optimal tester time and memory and collect enough fail data to provide acceptable diagnosis quality. In this paper we have presented a methodology for fail data collection and discussed the tester overheads for LBIST logic diagnosis.