Decoupling Capacitor Placer Algorithm with Routing and Area Consideration in VLSI Layout Design

Thomas Fong Chee Goh,  Jonathan Yoong Seang Ong,  Chun-Keong Lee


Conventional manual placement for decoupling capacitance (decap) is very time consuming and may lead to unavoidable human errors. In VLSI design environments there is a critical need to have an automated way via CAD tools, particularly to ensure quick turn-around times in the face of strong time-to-market pressures. Unfortunately, existing placer algorithms work best on rectangle placement regions, but are less efficient when working on polygon placement regions with more than 4 vertices. Therefore, in this paper, we present and propose a decap placer using new placement algorithm named Size and Level oriented algorithm (SL). This decap placer is implemented with routing and area consideration which works efficiently on both rectangle and polygon placement regions. Furthermore, different placement orientations are implemented as well in this decap placer for better decaps placement coverage. In this proposed SL decap placer, it first studied the placement region and defined it using the region defining algorithms. This region defining algorithm is important while dealing with polygon placement region. Next, the placer will place the decaps over the defined region effectively. While placing, in order to maximize the decap population, placer will consider and study the area to start placing the capacitor from biggest size until the smallest size. Placer at the same time will take consideration on the routing as well to take care of the connectivity between placed decaps and the metal overlapping to avoid the metal shortage with top routing metal. Finally, we further improved the coverage of decaps placer by implementing different placement orientation.