NBTI-induced 8-Bit DAC circuit mismatch in System-On-Chip (SoC)

Mohd Azman Abdul Latif1,  Dr Noohul Basheer Zain Ali2,  Dr Fawnizu Azmadi Hussin2

1Intel Corporation, 2University of Technology PETRONAS


This paper focuses on Negative Bias Temperature Instability (NBTI) awareness to the circuit designer for reliable design of the System-On-a-Chip (SoC) analog circuit. The reliability performance of all matched pair such as current source and differential pair circuits, utilizing Bandgap Reference circuit, is at the mercy of aging differential. Aging simulation (AgingSim) is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliability-critical device and NBTI is the most critical failure mechanism for analog circuit performance in sub-micrometer CMOS technology. This paper provides a complete reliability simulation analysis of an 8 bit Cathode-Ray-Tube (CRT) Digital-Analog-Converter (DAC) and analyze the effect of NBTI using aging simulation tool. It suggests key points that the NBTI failure rate varies as a function of voltage and temperature. NBTI is the most critical failure mechanism in sub-micrometer CMOS technology. Burn-In stress plays an important role in verifying the robustness of circuit design. A defect after Burn-In stress can cause performance degradation as well as design errors.