A Systems Approach to Verification using Hardware Acceleration

Sharad Kumar,  Sainath Shanbhag,  Gaurav Verma,  Mohit Mongia

Freescale Semiconductor


The increasing complexity of system-on-chip devices has made verification an extremely difficult and time consuming task. Additionally, there is the pressure of time-to-market that is faced by all semiconductor companies. Some of the functional complexity of such devices has made it necessary to run system level sequences that were typically run only in post-silicon phase earlier – ideally, in the pre-silicon stage. However, the effective speeds of simulators used during functional verification do not lend well to running system level tests. In this paper we will describe how a hardware accelerator was used to execute system level tests. We will share some of the results seen and some of the design issues that were detected using such an approach. We have illustrated this approach choosing three distinct areas of (i) secure boot, (ii) built-in-self-test sequences, and (iii) scan testing. We also believe that going to a system level apporach using hardware acceleration helps to find several difficult corner case issues that remain undetected using other verification approaches.